Specifications
Table Of Contents
- Title Page
- Table of Contents
- List of Figures
- List of Tables
- 1 Introduction
- 2 Installation
- 3 Navigating the LCD Display Screens
- 3.1 Basic Operating Procedure
- 3.2 Starting Point: The Main LCD Touch Screen
- 3.3 LCD Display Flow Chart
- 3.4 Details of the Exciter Status Screens
- 3.4.1 System Status Screen
- 3.4.2 Transport Stream Status Screen
- 3.4.3 Adaptive Processing Board Status Screen
- 3.4.4 Digital Processing Screens
- 3.4.4.1 Modulator Board Status, Screen 1/2
- 3.4.4.2 ADC and DAC Boards Status, Screen 2/2
- 3.4.4.3 FLO FPGA Status, Summary, Screen 1/5
- 3.4.4.4 FLO FPGA, GPS & Clock Status, Screen 2/5
- 3.4.4.5 FLO FPGA, Transport Stream Status, Screen 3/5
- 3.4.4.6 FLO FPGA, SFN FIFO Status, Screen 4/5
- 3.4.4.7 FLO FPGA, MTI Status, Screen 5/5
- 3.4.5 IF & RF Processing Status Screens
- 3.4.6 System Control Status Screens
- 3.5 Built In Tests
- 3.6 Details of the System Setup Screens
- 3.7 RTAC Operating Procedures, Main Screen.
- 4 Theory of Operation
- 5 Maintenance and Troubleshooting
- 5.1 Exciter Maintenance
- 5.2 Loading Software
- 5.3 Default Settings For DIagnostics Screens
- 5.4 Typical Settings for the More Critical Exciter Setups
- 5.5 Exciter Troubleshooting Flow Charts
- 5.6 General Troubleshooting
- 5.7 System Troubleshooting
- 5.8 Exciter Troubleshooting
- 6 Parts List
- Appendix A Exciter GUI Screen Captures

APEX™ Exciter Incorporating FLO™ Technology
Details of the System Setup Screens Navigating the LCD Display Screens
2604s300.fm
03/08/07 888-2604-001 Page: 3-35
WARNING: Disconnect primary power prior to servicing.
3.6.2 Exciter Setup Screen
ExciterSetup.bmp
Figure 3-32 Exciter Setup Screen
Refer to Figure 3-32, Exciter Setup Screen. The following ia a list of entries on the Exciter
setup screen.
• Power Limit. This adjustable S/W power limit will act as a clamp and will not allow
the user to set the power above this limit either locally on the exciter main screen or
remotely via the external I/O board raise/lower input. The range of this control is 0 to
250 mW.
• GPS Reference, refers to External or Internal GPS receiver use.
External is the normal mode. If used, it requires an external 1PPS input at the rear
panel connector.
Loss of the 1PPS will cause a Digital Status hardware switch fault (lights red) and the
Main Screen > Status > Digital Processing > FLO FPGA Registers will show fault.
Down Converter Status Diagnostics, See Section 3.4.5.4.1, Down Converter Diagnostics, on page 3-24
RF Sample Select Automatic Normal
RF Sample AGC Enabled Normal
Controller Status Diagnostics, See Section 3.4.6.1.1, Controller Board Diagnostics, on page 3-26
BIT Fifo Test Pattern Disabled Normal
DSP/FPGA S/W Watchdog Disabled Normal
External I/O Status Diagnostics, See Section 3.4.6.2.1, External I/O Diagnostics, on page 3-28
Analog Loopback Disabled Normal, but can be useful for analog input and
output testing, see technical manual.
Analog Output A 0
Analog Output B 0
Table 3-3 Settings Resulting From Restore Defaults Activation.