Specifications
Table Of Contents
- Title Page
- Table of Contents
- List of Figures
- List of Tables
- 1 Introduction
- 2 Installation
- 3 Navigating the LCD Display Screens
- 3.1 Basic Operating Procedure
- 3.2 Starting Point: The Main LCD Touch Screen
- 3.3 LCD Display Flow Chart
- 3.4 Details of the Exciter Status Screens
- 3.4.1 System Status Screen
- 3.4.2 Transport Stream Status Screen
- 3.4.3 Adaptive Processing Board Status Screen
- 3.4.4 Digital Processing Screens
- 3.4.4.1 Modulator Board Status, Screen 1/2
- 3.4.4.2 ADC and DAC Boards Status, Screen 2/2
- 3.4.4.3 FLO FPGA Status, Summary, Screen 1/5
- 3.4.4.4 FLO FPGA, GPS & Clock Status, Screen 2/5
- 3.4.4.5 FLO FPGA, Transport Stream Status, Screen 3/5
- 3.4.4.6 FLO FPGA, SFN FIFO Status, Screen 4/5
- 3.4.4.7 FLO FPGA, MTI Status, Screen 5/5
- 3.4.5 IF & RF Processing Status Screens
- 3.4.6 System Control Status Screens
- 3.5 Built In Tests
- 3.6 Details of the System Setup Screens
- 3.7 RTAC Operating Procedures, Main Screen.
- 4 Theory of Operation
- 5 Maintenance and Troubleshooting
- 5.1 Exciter Maintenance
- 5.2 Loading Software
- 5.3 Default Settings For DIagnostics Screens
- 5.4 Typical Settings for the More Critical Exciter Setups
- 5.5 Exciter Troubleshooting Flow Charts
- 5.6 General Troubleshooting
- 5.7 System Troubleshooting
- 5.8 Exciter Troubleshooting
- 6 Parts List
- Appendix A Exciter GUI Screen Captures
APEX™ Exciter Incorporating FLO™ Technology
Navigating the LCD Display Screens Details of the Exciter Status Screens
Page: 3-26 888-2604-001 03/08/07
WARNING: Disconnect primary power prior to servicing.
3.4.6.1 Controller Board Status Screen
ControllerStatus.bmp
Figure 3-24 Controller Board Status Screen
The Controller Board screen is shown in Figure 3-24, with screen entries listed below.
• Temp: This is the ambient air temperature of the digital (bottom) side of the exciter.
• 3.3 Vdc: This is the output of the 3.3 V dc to dc converter.
• 5 Vdc: This is the board input voltage from the main power supply.
• RTC battery: (OK or FAULT) Fault means battery is low and needs replaced.
• MPC823 PLL: (Ok or FAULT) This is the lock status of the internal PLL of the
MPC823 micro controller on the controller board. It indicates the internal 75 MHz
clock is locked to the 32.768 KHz crystal oscillator.
• Board Rev: Board revision for the Controller board.
• CPLD Rev: Revision level of the CPLD in the controller board.
• EEPROM: (Ok or FAULT) This EEPROM is used to save the user entered menu se-
lection from the various LCD screens.
• Boot Rev: Boot code revision level for the controller board.
• APP Rev: Micro controller application code revision level on the controller board.
3.4.6.1.1 Controller Board Diagnostics
A Bit FIFO Test Pattern function is available on the Controller Board Diagnostics screen.
This function is used by engineering and must remain disabled. If enabled, it will block the
normal signal flow.
The DSP/FPGA S/W Watchdog is also available on the Controller Board Diagnostics
screen. This function is used by engineering and is normally disabled.