Specifications
Table Of Contents
- Title Page
- Table of Contents
- List of Figures
- List of Tables
- 1 Introduction
- 2 Installation
- 3 Navigating the LCD Display Screens
- 3.1 Basic Operating Procedure
- 3.2 Starting Point: The Main LCD Touch Screen
- 3.3 LCD Display Flow Chart
- 3.4 Details of the Exciter Status Screens
- 3.4.1 System Status Screen
- 3.4.2 Transport Stream Status Screen
- 3.4.3 Adaptive Processing Board Status Screen
- 3.4.4 Digital Processing Screens
- 3.4.4.1 Modulator Board Status, Screen 1/2
- 3.4.4.2 ADC and DAC Boards Status, Screen 2/2
- 3.4.4.3 FLO FPGA Status, Summary, Screen 1/5
- 3.4.4.4 FLO FPGA, GPS & Clock Status, Screen 2/5
- 3.4.4.5 FLO FPGA, Transport Stream Status, Screen 3/5
- 3.4.4.6 FLO FPGA, SFN FIFO Status, Screen 4/5
- 3.4.4.7 FLO FPGA, MTI Status, Screen 5/5
- 3.4.5 IF & RF Processing Status Screens
- 3.4.6 System Control Status Screens
- 3.5 Built In Tests
- 3.6 Details of the System Setup Screens
- 3.7 RTAC Operating Procedures, Main Screen.
- 4 Theory of Operation
- 5 Maintenance and Troubleshooting
- 5.1 Exciter Maintenance
- 5.2 Loading Software
- 5.3 Default Settings For DIagnostics Screens
- 5.4 Typical Settings for the More Critical Exciter Setups
- 5.5 Exciter Troubleshooting Flow Charts
- 5.6 General Troubleshooting
- 5.7 System Troubleshooting
- 5.8 Exciter Troubleshooting
- 6 Parts List
- Appendix A Exciter GUI Screen Captures
APEX™ Exciter Incorporating FLO™ Technology
Maintenance and Troubleshooting Exciter Troubleshooting
Page: 5-24 888-2604-001 03/08/07
WARNING: Disconnect primary power prior to servicing.
5.8.6.2 Adaptive Precorrector Board
This board uses several main screen chart memories, selected from the chart source of the
display setup screen. They are listed below.
The FLO Ref memory is located at the input of the Adaptive precorrector board.
The FLO w/RTAC memory monitors the output of the board. This is the signal that drives
the DAC to produce the 11.1 MHz 1st IF.
Three intermediate memories are collected as the signal travels through the board. They are
used for adaptive processing. In the order of travel (from input to output) they are the C, D,
and J memories. Due to pre compensation applied to the signals, the displays from these
memories and the FLO w/RTAC memory may appear distorted. If all three RTAC samples
(on the main screen) are put is Bypass mode, the signals should appear similar to the FLO
Ref memory signal.
5.8.6.3 ADC and DAC Boards
Troubleshooting defective ADC or DAC boards is covered in Section 5.8.5.1, Checking
Operation of the Entire Digital Tray, on page 5-21.
5.8.6.4 Front Panel Board
Troubleshooting a defective front panel board is covered in Section 5.8.2, Dark Screen, on
page 5-19.
5.8.6.5 Controller Board
Since the operation of most of the other bards (except for the power supply) are effected by
the controller board, it could cause faulty operation of any or all these boards. If the above
troubleshooting does not solve the problem, it could be caused by a faulty controller board.
A faulty controller board may be indicated by a bad front panel display. If the front panel
display is operating, the controller board status screen can be checked. This is the first
screen of the four system control status screens.
1 Check for front panel display and LEDs. If no activity, check the controller board.
2 Controller board has two green LEDs for the dc power. DS1 = +3.3 Vdc and DS4 =
+5Vdc.
3 If LEDs 0 through 7 are scrolling, the fault is probably a cable going to the front panel
board or the board itself.
A If the LEDs are not scrolling, check the +5 volt power to board at test point
10 and the +3.3 volt power at test point 5. If the +5 Vdc voltage is valid, re-
place the board.