Specifications
Table Of Contents
- Title Page
- Table of Contents
- List of Figures
- List of Tables
- 1 Introduction
- 2 Installation
- 3 Navigating the LCD Display Screens
- 3.1 Basic Operating Procedure
- 3.2 Starting Point: The Main LCD Touch Screen
- 3.3 LCD Display Flow Chart
- 3.4 Details of the Exciter Status Screens
- 3.4.1 System Status Screen
- 3.4.2 Transport Stream Status Screen
- 3.4.3 Adaptive Processing Board Status Screen
- 3.4.4 Digital Processing Screens
- 3.4.4.1 Modulator Board Status, Screen 1/2
- 3.4.4.2 ADC and DAC Boards Status, Screen 2/2
- 3.4.4.3 FLO FPGA Status, Summary, Screen 1/5
- 3.4.4.4 FLO FPGA, GPS & Clock Status, Screen 2/5
- 3.4.4.5 FLO FPGA, Transport Stream Status, Screen 3/5
- 3.4.4.6 FLO FPGA, SFN FIFO Status, Screen 4/5
- 3.4.4.7 FLO FPGA, MTI Status, Screen 5/5
- 3.4.5 IF & RF Processing Status Screens
- 3.4.6 System Control Status Screens
- 3.5 Built In Tests
- 3.6 Details of the System Setup Screens
- 3.7 RTAC Operating Procedures, Main Screen.
- 4 Theory of Operation
- 5 Maintenance and Troubleshooting
- 5.1 Exciter Maintenance
- 5.2 Loading Software
- 5.3 Default Settings For DIagnostics Screens
- 5.4 Typical Settings for the More Critical Exciter Setups
- 5.5 Exciter Troubleshooting Flow Charts
- 5.6 General Troubleshooting
- 5.7 System Troubleshooting
- 5.8 Exciter Troubleshooting
- 6 Parts List
- Appendix A Exciter GUI Screen Captures
APEX™ Exciter Incorporating FLO™ Technologyr
DC Power Distribution Theory of Operation
2604s400.fm
03/08/07 888-2604-001 Page: 4-17
WARNING: Disconnect primary power prior to servicing.
• +15 Volt Float leaves UDC interface board at J5 pin 2, the return is J5 pin 1.
4.5.3.3 Down Converter Board Power
The down converter board receives its dc voltages (+/- 15 Vdc and +8 Vdc) from the UDC
interface board via connector J8. The down converter board supplies are listed below.
• +15 Vdc: Input power from UDC interface board via connector J8 pin 1
• -15 Vdc: Input power from UDC interface board via connector J8 pin 3
• 8 Vdc: Input power from UDC interface board via connector J8 pin 5
• An on board regulator produces -5 Vdc from the -15 Vdc supply
• An on board regulator produces +5 Vdc from the +8 Vdc supply.
The following ia a list of entries on the down converter board status screen.
• +15 Vdc: Input power
• -15 Vdc: Input power
• +8 Vdc: Input power.
4.5.3.4 PLL Board Power
The PLL (phase lock loop) board receives its dc voltages (+/- 15 Vdc and +8 Vdc) from the
UDC interface board via connector J1, as listed below.
• +15 Vdc: Input power from UDC interface board via connector J1 pin 1
• -15 Vdc: Input power from UDC interface board via connector J1 pin 3
• 8 Vdc: Input power from UDC interface board via connector J1 pin 5
Several on board regulators are used to achieve low noise and excellent isolation between
the PLL board digital input/output circuits, 10 MHz reference oscillator, 128.9 MHz 1st
local oscillator (LO), and the 2ns local oscillator. This board contains seven on board +5
Vdc regulators, one +12 Vdc regulator, six +3.3 Vdc regulators, one +2.5 Vdc regulator,
and one +1.8Vdc regulator.
The following ia a list of entries on the PLL board status screen.
• +15 Vdc: Input power from UDC interface board via connector J1 pin 1.
• -15 Vdc: Input power from UDC interface board via connector J1pin 3.
• 8 Vdc: Input power from UDC interface board via connector J1pin 5.