Specifications
Table Of Contents
- Title Page
- Table of Contents
- List of Figures
- List of Tables
- 1 Introduction
- 2 Installation
- 3 Navigating the LCD Display Screens
- 3.1 Basic Operating Procedure
- 3.2 Starting Point: The Main LCD Touch Screen
- 3.3 LCD Display Flow Chart
- 3.4 Details of the Exciter Status Screens
- 3.4.1 System Status Screen
- 3.4.2 Transport Stream Status Screen
- 3.4.3 Adaptive Processing Board Status Screen
- 3.4.4 Digital Processing Screens
- 3.4.4.1 Modulator Board Status, Screen 1/2
- 3.4.4.2 ADC and DAC Boards Status, Screen 2/2
- 3.4.4.3 FLO FPGA Status, Summary, Screen 1/5
- 3.4.4.4 FLO FPGA, GPS & Clock Status, Screen 2/5
- 3.4.4.5 FLO FPGA, Transport Stream Status, Screen 3/5
- 3.4.4.6 FLO FPGA, SFN FIFO Status, Screen 4/5
- 3.4.4.7 FLO FPGA, MTI Status, Screen 5/5
- 3.4.5 IF & RF Processing Status Screens
- 3.4.6 System Control Status Screens
- 3.5 Built In Tests
- 3.6 Details of the System Setup Screens
- 3.7 RTAC Operating Procedures, Main Screen.
- 4 Theory of Operation
- 5 Maintenance and Troubleshooting
- 5.1 Exciter Maintenance
- 5.2 Loading Software
- 5.3 Default Settings For DIagnostics Screens
- 5.4 Typical Settings for the More Critical Exciter Setups
- 5.5 Exciter Troubleshooting Flow Charts
- 5.6 General Troubleshooting
- 5.7 System Troubleshooting
- 5.8 Exciter Troubleshooting
- 6 Parts List
- Appendix A Exciter GUI Screen Captures

APEX™ Exciter Incorporating FLO™ Technologyr
APEX Exciter Analog Assembly Overview Theory of Operation
2604s400.fm
03/08/07 888-2604-001 Page: 4-7
WARNING: Disconnect primary power prior to servicing.
Figure 4-4 Exciter Output Spectral Response, RTAC Bypassed
4.4 APEX Exciter Analog Assembly Overview
The analog assembly (top side of exciter) contains the following subassemblies. Refer to
Figure 5-1, on page 5-2 for a view of the analog (top side) assembly circuit board layout.
• A1 - Exciter power supply board
• B1 - Cooling fan.
• A6 - UDC (up/down converter interface) board
• A4 - PLL (phase lock loop) board
• A3 - Up Converter board
• A2 - Output Amplifier board
• A5 - Down Converter board.
Refer to Figure 4-2 for a block diagram of the APEX exciter.
The up-converter accepts a 11.1 MHz IF from the DAC (digital to analog converter board
(A12) connector J3. The up converter converts the signal in two stages to an on channel
UHF output. It may be configured (via the front panel touch screen) to place the exciter
output at any desired center frequency within selected portions of the UHF spectrum.
Local oscillators used for up and down conversions are generated via low noise phase
locked loops. All frequencies are referenced to a common 10 MHz standard, which is
locked to the GPS 1PPS (pulse per second) signal.
A
SWT 30 ms
*
AVG
*1 R
M
Att 25 dBRef -1 dBm
Center 719 MHz Span 10 MHz1 MHz/
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Response
Shoulder
Response
Shoulder