Specifications
Table Of Contents
- Title Page
- Table of Contents
- List of Figures
- List of Tables
- 1 Introduction
- 2 Installation
- 3 Navigating the LCD Display Screens
- 3.1 Basic Operating Procedure
- 3.2 Starting Point: The Main LCD Touch Screen
- 3.3 LCD Display Flow Chart
- 3.4 Details of the Exciter Status Screens
- 3.4.1 System Status Screen
- 3.4.2 Transport Stream Status Screen
- 3.4.3 Adaptive Processing Board Status Screen
- 3.4.4 Digital Processing Screens
- 3.4.4.1 Modulator Board Status, Screen 1/2
- 3.4.4.2 ADC and DAC Boards Status, Screen 2/2
- 3.4.4.3 FLO FPGA Status, Summary, Screen 1/5
- 3.4.4.4 FLO FPGA, GPS & Clock Status, Screen 2/5
- 3.4.4.5 FLO FPGA, Transport Stream Status, Screen 3/5
- 3.4.4.6 FLO FPGA, SFN FIFO Status, Screen 4/5
- 3.4.4.7 FLO FPGA, MTI Status, Screen 5/5
- 3.4.5 IF & RF Processing Status Screens
- 3.4.6 System Control Status Screens
- 3.5 Built In Tests
- 3.6 Details of the System Setup Screens
- 3.7 RTAC Operating Procedures, Main Screen.
- 4 Theory of Operation
- 5 Maintenance and Troubleshooting
- 5.1 Exciter Maintenance
- 5.2 Loading Software
- 5.3 Default Settings For DIagnostics Screens
- 5.4 Typical Settings for the More Critical Exciter Setups
- 5.5 Exciter Troubleshooting Flow Charts
- 5.6 General Troubleshooting
- 5.7 System Troubleshooting
- 5.8 Exciter Troubleshooting
- 6 Parts List
- Appendix A Exciter GUI Screen Captures
APEX™ Exciter Incorporating FLO™ Technology
Theory of Operation APEX Exciter Digital Assembly Overview
Page: 4-2 888-2604-001 03/08/07
WARNING: Disconnect primary power prior to servicing.
Figure 4-1 APEX Exciter/ Transmitter - RF Interconnection Block Diagram
4.3 APEX Exciter Digital Assembly Overview
Figure 4-2 is an overall block diagram of the APEX exciter. Refer to it while studying the
exciter digital assembly, also, refer to Figure 5-2, on page 5-3 for a view of the physical
layout digital tray.
The APEX exciter digital assembly (bottom side of exciter) accepts dc supply voltages
from the power supply board (located in the top, analog side of the exciter) and an ASI
transport stream as input. This tray provides a fully modulated OFDM (orthogonal
frequency division multiplexed) first IF output centered at 11.1 MHz.
The digital assembly also performs RTAC™ (real time adaptive correction) pre-correction
on the signal following the modulation and spectral filtering processes. Two down
converted samples from various locations along the transmitter system are compared the
output of the modulator board to shape the pre-corrected RF output signal of the exciter.
This pre-corrected signal minimizes the nonlinear and linear distortions of PA and high
power filter.
The digital assembly consists of 6 circuit boards:
• A7 - UHF External I/O (input/output) Board
• A8 - Controller Board
• A9 - Adaptive Precorrector board
• A11 - ADC (analog to digital converter) board
• A12 - DAC (digital to analog converter) board
• A13 - FPGA Modulator board
Signal flow from input to output of the digital (bottom) assembly of the exciter may be
followed by referring to Figure 4-2. The ASI transport stream is input to the FPGA
Modulator board, A13.
The modulator board output passes through the controller board (A8) and on to the
adaptive precorrector board (A9).
PA
Output
Coupler
High
Power
PA
Cabinet
Filter
Coupler
APEX
Exciter
RF output
to Antenna
PA (Non-Linear)
RF Feedback Sample
HPF Output (Linear)
RF Feedback Sample
Transport
Stream
Input
Exciter RF
Output