Specifications

NEWS 2012
www.lauterbach.com2
Virtual Targets
Today virtual targets are increasingly being used to
start software development long before the first hard-
ware prototypes become available. As soon as a
virtual target is available, debugging of the driver, the
operating system, and the application can begin.
For debugging and tracing, most virtual targets have
their own API. If this is not the case, the standardized
MCD-API (
http://www.lauterbach.com/mcd_api.html)
can be used. Many new projects today use multicore
chips. Consequently, Lauterbach has expanded its mul-
ticore debugging support for virtual targets since 2011.
Pre-Silicon Validation
For semiconductor manufacturers, it is important to
validate the design of their processors or SoCs before
actual production. Individual sections are intensely
tested, for example: the JTAG interface, the entire core,
or the interaction between core and peripherals.
For this testing, you traditionally used an emulator for
the silicon (e.g. Palladium) or FPGA prototypes, con-
nected to the hardware-based TRACE32 debug tools.
This would run much slower than the real processors.
Today, you can perform first validations of Verilog or
SystemC models directly on a PC or a workstation.
With pure software validation you cannot use debug
hardware. Therefore, Lauterbach added a Verilog
Back-End to its software in 2011. This simulates a
JTAG interface at the signal level (see figure 1).
The integration of TRACE32 tools into the pre-silicon
validation forms an important part of the early support
for the latest processors and SoCs:
• Testedtoolsarereadybeforetherstsiliconleaves
the factory.
• Expert knowledge of the new processor/SoC is
available and can be accessed by the customer.
• Start-up scripts for the TRACE32 debugger are
available.
60+ Supported Processor Architectures
Lauterbach has tools available for all the common
processors or SoCs on the embedded market. In fact
Lauterbach is the only provider of tools for many cores.
Standard controllers, DSPs, FPGA softcores, configu-
rable cores - everything can be combined into a multi-
core chip and debugged with a TRACE32 tool.
In 2011, Lauterbach also added support for numerous
new processors and multicore chips. For an overview,
see the table on page 4.
Test and Analysis Functions
Each phase of a project requires its own test and
analysis functions. To provide this, the TRACE32
PowerView GUI includes an extensive selection of
commands and menus. Boundary scan commands
(see figure 2), core detection commands and com-
mands for manipulating the JTAG pins are some
examples of low-level commands.
Fig. 1: For each user entry in TRACE32 Front-End, Verilog Back-End produces JTAG signals for validation of the model.
Verilog model
TRACE32
Actuator
(shared library)
.DLL /.SO
TRACE32 Front-End for ARM
TRACE32
Verilog Back-End
for Cortex-A/-R
.V
JTAG TAP
.V
Cortex-A
.V
.V
Trigger
Verilog Simulator for Cortex-A
Run-time
counter
JTAG
Reset
TRACE32
Actuator
.V
Verilog
Procedural
Interface
Named
pipe