Specifications

NEWS 2012
www.lauterbach.com12
Troubleshooting, performance tuning and code-
coverage - all of these can be performed quickly
and precisely on an embedded system if the ad-
equate trace analysis is provided. In 2011, Lauter-
bach explored new paths to enable optimized trace
analyses for the Cortex-M3/M4 processors.
Combining ETM and ITM
For Cortex-M3/M4 processors, trace information can
be generated from two different sources (see fig-
ure 17). The ETMv3 generates information about the
executed instructions. The ITM generates information
about the performed read/write accesses assisted by
the Data Watchpoint and Trace Unit (DWT).
The ITM trace packages for read/write accesses con-
tain the following information: data address, data value,
program counter.
Through analysis of the program counter, the data
accesses which are separately generated can be
seamlessly integrated into the program sequence (see
gure15),whichinturnleadstosignicantlysimpler
error location. The cause of an error such as an incor-
rect data value being written into an address can be
easily found if the write accesses are embedded into
the overall program trace.
OS-Aware Tracing
If an operating system is running on the Cortex-M3/
M4, task switch information becomes essential for the
trace analysis.
Intelligent Trace Analyses for Cortex-M3/M4
Instruction flow with task switches (ETM&ITM)
Timing diagram for task switches (ITM) Timing diagram for task MIPS (ETM&ITM)
Call tree for task "sens1" (ETM&ITM)
Fig. 16: Through the combination of ETM and ITM trace data, extensive trace analysis can be provided for the eCos operating system.
Instruction flow with data accesses (ETM&ITM)
Fig.15: BycombiningETMandITMtracedata,read/writeaccessescanbe
integrated seamlessly into the program sequence.