Specifications

11
TMC as Embedded Trace FIFO
Inspections of the trace data streams being exported
by the TPIU have shown that the bandwidth of most
trace ports is large enough for normal operation. Over-
load, and therefore loss of trace data, only happens
when peaks occur.
The Trace Memory Controller can be integrated into
the trace infrastructure of the SoCs, so that the Trace
Memory Controller acts as an Embedded Trace FIFO
and cushions peaks in the load on the TPIU (see fig-
ure 13). This ETF is designed so that no trace data
loss can occur. The size of the ETF can be freely de-
nedfrom512Bytesto4GBytes.
Both integrations of the Trace Memory Controller in
the trace infrastructure depicted are simple examples.
Of course, you can build the TMC IP block into the
CoreSight system in much more complex and flexible
ways.
Modifications in TRACE32
As you would expect, Lauterbach has to modify the
TRACE32 software for the configuration and handling
of the Trace Memory Controller. This applies especially
when the Trace Memory Controller is integrated in the
SoC using new, previously unsupported ways. The
TRACE32 user only needs to configure the basic ad-
dress for the TMC. Then all the proven trace display
and analysis features can be used as usual.
TMC as Router to High-Speed Link
The idea of moving away from dedicated trace ports
has long been discussed within the embedded com-
munity. There are certainly several good arguments for
this move.
For the first time CoreSight traces can now connect
to a high-speed standard interface by using the Trace
Memory Controller. USB or Ethernet interfaces are
common favorites, especially as they are available in
many end products. Ideally, the external trace tool will
share the interface with the other connected devices.
Within the SoC, the TMC operates as Embedded Trace
Router and has the task of passing on the trace data
through the AXI bus for the export to the IP of the high-
speed interface (see figure 14).
This new method of trace export will need completely
new trace tools. Lauterbach is currently in close contact
with leading semiconductor manufacturers to develop
the appropriate tools for this switch in technology.
• Openforusewithallcoreswhichcanbeintegrated
into CoreSight; Lauterbach offers debug solutions
for all ARM/Cortex cores and for numerous DSPs,
as well as for configurable cores.
• Supportforasymmetricmultiprocessing(AMP)and
symmetric multiprocessing (SMP)
•
Debugging via JTAG interface and 2-pin Serial Wire
Debug
• Synchronizeddebuggingofallcores
• SupportfortheCoreSightCrossTriggerMatrix
• Supportforalltypesoftracemacrocells
(ETM,PTM,HTM,ITM,STM,andmore)
• Toolsforparallelandserialtraceports
• Multicoretracing
TRACE32 CoreSight Features
Trace bus (ATB)
Trace Memory Controller
in FIFO mode
SRAM
TPIU
Fig. 13: In FIFO mode, the Trace Memory Controller can cushion load
peaks on the TPIU. By doing this, trace data loss can be avoided.
Trace Memory Controller
in Router mode
SRAM
AXI
High-speed link
(USB, Ethernet, ...)
Trace bus (ATB)
Fig. 14: In Router mode, the Trace Memory Controller forwards the trace
data for the export to a high-speed standard interface.