Specifications

NEWS 2012
www.lauterbach.com10
The new CoreSight Trace Memory Controller pro-
vides SoC designers with more design options for
the trace infrastructure. TRACE32 already has sup-
port for the first designs which use the TMC.
Through CoreSight, the diagnosis data needed for
the analysis of SoC-internal processes is produced
by ‘trace macrocells’. There are three types of trace
macrocells:
• Core trace macrocells are assigned to a core and
generate trace information about the instructions
processed by that core. Information about process
switches and load/store operations is generated
depending on the design of the trace cell.
• Bus trace macrocells are firmly assigned to a bus
and generate trace information on data transfers
that occur on the bus.
• System trace macrocells generate trace informa-
tion for hardware trigger (system event tracing) or
provide diagnostic information produced by code
instrumentation of the application software.
The CoreSight Funnel combines all of the trace data
into a single data stream (see figure 11). This trace
data stream is then either stored in an on-chip mem-
ory buffer (ETB) or exported to an external tool using
a trace port (TPIU). The IP for CoreSight trace being
implemented today is sometimes pushed to the limit
when dealing with complex multicore SoCs that con-
tain many trace macrocells.
• ETB: The on-chip trace memory is often too small to
record enough trace data for any meaningful future
analysis. The typical size for the ETB is still between
4and16KByte.
• TPIU: System states may occur where more trace
data is being generated than the trace port can output.
The CoreSight design is such that trace data from the
trace macrocells is only taken over if the trace data
can be exported by the TPIU. If the trace data gener-
ated remains in the trace macrocells for too long, the
FIFOs there can overflow and important data may
be lost.
The new CoreSight Trace Memory Controller should
provide a solution for both of the above scenarios.
TMC as Embedded Trace Buffer
To be able to store more trace data on-chip for later
analysis, the chip manufacturer can theoretically con-
nect up to 4 GByte of SRAM to the Trace Memory Con-
troller (see figure 12).
CoreSight Trace Memory Controller
ARM CoreSight
With CoreSight, ARM makes available an exten-
sive set of IP blocks, which enables SoC designers
to build a custom debug and trace infrastructure.
A single debug interface is enough to control and
coordinate all cores of the SoC, as well as access
all memory.
One trace interface is sufficient for providing diag-
nostic data about the processes occurring within the
SoCs without any impact on real-time performance.
Core
trace
System
trace
Bus
trace
TPIU ETB
Funnel
Trace bus (ATB)
Fig. 11: CoreSight Funnel combines all trace data produced by trace
macrocells into a single data stream.
Trace Memory Controller
in ETB mode
SRAM
Trace bus (ATB)
Fig. 12: In ETB mode, the Trace Memory Controller can make up to 4 GByte
of on-chip trace memory available.