Specifications

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CONTENTS

New Supported Processors 4

Nexus-Trace for Small Package Format Cores 5

Checking JTAG Signals 6

Enhancements to Target OS-Awareness 6

Code-Coverage – Simplified 7

CoreSight Trace Memory Controller 10

Trace Analyses for Cortex-M3/M4 12

Simulink

Integration 14

UEFI BIOS Debugging with TRACE32 16

www.lauterbach.com

DEBUGGER, REAL-TIME TRACE, LOGIC ANALYZER

NEWS 2012

Embedded designs are becoming ever more com-

plex and time to market is getting shorter. To meet

these challenges many project managers now rely on

debug and trace tools that can accompany developers

through all phases of the project.

TRACE32, the debug and trace tool family from Lauter-

bach provides a consistent concept and environment

which can be further extended with user customizable

scripts. This helps to shorten the familiarization pro-

cess and makes time for the actual development work.

Developers with practical knowledge gained from

more than 10 years experience with TRACE32 are

quite common. So, what makes TRACE32 different?

• Hardware-andsoftware-basedtools

• Earlysupportfornewprocessors

• Largeportfolioofsupportedprocessors

• Extensivetestandanalysisfunctions

• Seamlessintegrationintotheembeddedtoolchain

Hardware and Software Tools

The core business of Lauterbach is the design and

manufacture of hardware-based debug and trace tools.

In addition Lauterbach has also offered logic analyzers

for over 20 years. The key feature of TRACE32 logic

analyzers is seamless integration within the hardware-

based debug and trace tools. For a typical application

using the logic analyzer integrated in PowerTrace II

read the article “Checking JTAG Signals” on page 6.

Fast, efﬁcient computers mean that more simulation

and validation is being undertaken on PC and worksta-

tions. In the embedded world the pre-silicon software

development on virtual targets has become the norm.

For this phase of the project Lauterbach can provide

pure software solutions.

A Debugger for all Phases of the Project

Summary of content (16 pages)

PAGE 1
NEWS 2012 DEBUGGER, REAL-TIME TRACE, LOGIC ANALYZER A Debugger for all Phases of the Project Embedded designs are becoming ever more complex and time to market is getting shorter. To meet these challenges many project managers now rely on debug and trace tools that can accompany developers through all phases of the project. for over 20 years. The key feature of TRACE32 logic analyzers is seamless integration within the hardwarebased debug and trace tools.
PAGE 2
Virtual Targets Today virtual targets are increasingly being used to start software development long before the first hardware prototypes become available. As soon as a virtual target is available, debugging of the driver, the operating system, and the application can begin. For debugging and tracing, most virtual targets have their own API. If this is not the case, the standardized MCD-API (http://www.lauterbach.com/mcd_api.html) can be used. Many new projects today use multicore chips.
PAGE 3
Scan chain configuration Since July 2011, Lauterbach has included the option of exporting trace information in Prism format, enabling the CriticalBlue tools to work with the trace recorded by the actual operation of the code. The article “Simulation and Reality Come Closer Together” on page 14 thoroughly describes another innovation – the integration between MATLAB Simulink® and TRACE32. Fig. 2: Boundary-Scan commands are available for commissioning the hardware.
PAGE 4
New Supported Processors New Derivatives Altera 4 Cortex-A / -R • FPGA with Cortex-A9 MPCore as Hardcore MIPS32 • MP32 AppliedMicro PPC44x • 86290 / 491 / 791 Q2/2012 ARM Cortex-A / -R • Cortex-A7/Cortex-A7 MPCore • Cortex-A15 • Cortex-A15 MPCore • Cortex-R5/Cortex-R5 MPCore • Cortex-R7/Cortex-R7 MPCore Beyond Semiconductor Beyond • BA22 Broadcom MIPS32 • BCM35230 • BCM63168, BCM63268 • BCM7231, BCM7358 Fujitsu Cortex-A / -R • MB9DF126, MB9EF126 IBM PPC44x •
PAGE 5
New Derivatives Samsung ARM7 • S3F4 Cortex-A / -R • S5PV310 Cortex-M • S3FM, S3FN ST-Ericsson Cortex-A / -R • A9500, A9540, M7400 MMDSP • A9500, A9540 STMicroelectronics MPC55xx/56xx • SPC56A80, SPC56HK Cortex-M • STM32F2xx, STM32F4xx Synopsys ARC • ARC EM4, ARC EM6 Tensilica Xtensa • BSP3, LX4, SSP16 Texas Instruments MSP430 • CC430Fxxx, MSP430FR5xxx • MSP430x1xx..MSP430x6xx Texas Instruments (Cont.
PAGE 6
Checking JTAG Signals Lauterbach’s PowerTrace II is equipped with an integrated logic analyzer and supplied with a standard digital probe. This enables 17 digital channels to be recorded with a sampling rate of up to 200 MHz. This logic analyzer has a save depth of up to 1024K samples and an example of its use would be the test of the JTAG signals during pre-silicon validation (see figures 6 and 7). JTAG signals Fig. 6: The recorded JTAG signals. JTAG protocol Fig.
PAGE 7
Code-Coverage – Simplified As of March 2011, TRACE32 trace information can be streamed to a host hard-disk from the running target. The large amount of program flow data which can result from this method, leads to a significant simplification of the code-coverage. Trace-based Code-Coverage Proof of statement coverage and condition coverage is often required to meet system quality specifications in industries such as medical and automotive.
PAGE 8
Fast Host Interface PowerTrace vs. PowerTrace II The amount of trace data that is exported via the trace port depends on the target system hardware. The number of cores, the number of trace port pins, and the trace clock speed are all important parameters. The protocol used by the core trace logic plays also an important role. For example, the ARM PTM protocol is more compact than the ARM ETMv3 protocol (see figure 9). The embedded software is another major variable.
PAGE 9
addresses. The trace source must also be configured, so that information is generated defining the virtual address space in which an instruction was located. For the ARM ETM/PTM, the amount of trace data can be further reduced: • The code-coverage analysis does not analyze or need time information. We therefore recommend configuring the TRACE32 trace tool so that the trace data is transferred to the host without time stamps. This reduces the amount of data by a third.
PAGE 10
CoreSight Trace Memory Controller The new CoreSight Trace Memory Controller provides SoC designers with more design options for the trace infrastructure. TRACE32 already has support for the first designs which use the TMC. Core trace Bus trace System trace Trace bus (ATB) ETB Fig. 11: CoreSight Funnel combines all trace data produced by trace macrocells into a single data stream. Through CoreSight, the diagnosis data needed for the analysis of SoC-internal processes is produced by ‘trace macrocells’.
PAGE 11
TMC as Embedded Trace FIFO Trace bus (ATB) Inspections of the trace data streams being exported by the TPIU have shown that the bandwidth of most trace ports is large enough for normal operation. Overload, and therefore loss of trace data, only happens when peaks occur. The Trace Memory Controller can be integrated into the trace infrastructure of the SoCs, so that the Trace Memory Controller acts as an Embedded Trace FIFO and cushions peaks in the load on the TPIU (see figure 13).
PAGE 12
Intelligent Trace Analyses for Cortex-M3/M4 Troubleshooting, performance tuning and codecoverage - all of these can be performed quickly and precisely on an embedded system if the adequate trace analysis is provided. In 2011, Lauterbach explored new paths to enable optimized trace analyses for the Cortex-M3/M4 processors. Instruction flow with data accesses (ETM&ITM) Combining ETM and ITM For Cortex-M3/M4 processors, trace information can be generated from two different sources (see figure 17).
PAGE 13
In order to receive information about task switches the following method can be used: Trace information on the write cycle in which the kernel writes the identifier for the current task on the corresponding OS variable can be generated using the ITM. As described above the write access information can be integrated seamlessly into the program flow trace. This improves the readability of the trace listing (see figure 16).
PAGE 14
Simulation and Reality Draw Closer Together It is now common to perform simulation and verification of designs before committing to hardware. This is why tools such as MATLAB® and Simulink® have made inroads as development software into the control engineering market. It can save a lot of time and effort if the control loop can be tested for the effects of many variables before finalizing the design.
PAGE 15
Simulink® TRACE32 PowerView Fig. 19: The block belonging to the selected source code line is marked in Simulink. TRACE32 debugger. These lines allow a simple correlation between the Simulink block and the lines in the source code. Navigation from Simulink® to TRACE32 A global TRACE32 menu and TRACE32 menus for blocks and signals are integrated into Simulink as ‘Simulink Customization Menus’. The TRACE32 debugger can be controlled from Simulink with the help of these menus.
PAGE 16
UEFI BIOS Debugging with TRACE32 A new TRACE32 extension for the Atom™ Debugger provides a complete debug capability of Insyde’s H2O UEFI BIOS. UEFI is the successor to the traditional PC BIOS. It functions as an interface between firmware and operating system managing the boot process. From poweron to takeover by the operating system, UEFI runs through various, clearly distinguished phases (see figure 21). As it is a JTAG-based tool, TRACE32 allows debugging to start from the reset vector.