User Guide
Table Of Contents
- MX46LS
- Hardware Installation
- About “Optional” and “Upgrade Optional”…
- JP14 Clear CMOS Data
- CPU Installation
- CPU Jumper-less Design
- CPU and System Fan Connector (with H/W Monitoring)
- JP28 USB Keyboard / Mouse Wakeup
- DIMM Sockets
- Front Panel Connector
- ATX Power Connector
- AC Power Auto Recovery
- IDE and Floppy Connector
- IrDA Connector
- AGP (Accelerated Graphic Port) Expansion Slot
- WOM (Zero Voltage Wake on Modem) Connector
- WOM by External BOX Modem
- WOM by Internal Modem Card
- WOL (Wake on LAN)
- Support 10/100 Mbps LAN onboard
- CNR (Communication and Network Riser) Expansion Slot
- PC99 Color Coded Back Panel
- Support 3 USB Ports
- CD Audio Connector
- Modem Audio Connector
- Front Audio Connector
- Dr. LED Connector (Upgrade Optional)
- Battery-less and Long Life Design
- Over-current Protection
- Hardware Monitoring
- Resettable Fuse
- 1500μF Low ESR Capacitor
- Layout (Frequency Isolation Wall)
- Pure Aluminum Heatsink
- Driver and Utility
- AWARD BIOS
- Overclocking
- Glossary
- AC97
- ACPI (Advanced Configuration & Power Interface)
- AGP (Accelerated Graphic Port)
- AMR (Audio/Modem Riser)
- Bonus Pack CD
- APM (Advanced Power Management)
- ATA (AT Attachment)
- ATA/66
- ATA/100
- BIOS (Basic Input/Output System)
- Bus Master IDE (DMA mode)
- CNR (Communication and Networking Riser)
- CODEC (Coding and Decoding)
- DDR (Double Data Rated) SDRAM
- DIMM (Dual In Line Memory Module)
- DMA (Direct Memory Access)
- ECC (Error Checking and Correction)
- EDO (Extended Data Output) Memory
- EEPROM (Electronic Erasable Programmable ROM)
- EPROM (Erasable Programmable ROM)
- EV6 Bus
- FCC DoC (Declaration of Conformity)
- FC-PGA (Flip Chip-Pin Grid Array)
- Flash ROM
- FSB (Front Side Bus) Clock
- I2C Bus
- IEEE 1394
- Parity Bit
- PBSRAM (Pipelined Burst SRAM)
- PC-100 DIMM
- PC-133 DIMM
- PC-1600 or PC-2100 DDR DRAM
- PCI (Peripheral Component Interface) Bus
- PDF Format
- PnP (Plug and Play)
- POST (Power-On Self Test)
- RDRAM (Rambus DRAM)
- RIMM (Rambus Inline Memory Module)
- SDRAM (Synchronous DRAM)
- Shadow E2PROM
- SIMM (Single In Line Memory Module)
- SMBus (System Management Bus)
- SPD (Serial Presence Detect)
- Ultra DMA
- USB (Universal Serial Bus)
- VCM (Virtual Channel Memory)
- ZIP file
- Troubleshooting
- Technical Support
- Product Registration
- How to Contact Us

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FSB Clock means CPU external bus clock.
CPU internal clock = CPU FSB Clock x CPU Clock Ratio
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See SMBus.
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IEEE 1394 is a low-cost digital interface originated by Apple Computer as a desktop LAN and developed by the IEEE 1394 working group.
The IEEE 1394 can transport data at 100, 200 or 400 Mbps. One of the solutions to connect digital television devices together at 200 Mbps.
Serial Bus Management provides overall configuration control of the serial bus in the form of optimizing arbitration timing, guarantee of
adequate electrical power for all devices on the bus, assignment of isochronous channel ID, and notification of errors. There are two type of
IEEE 1394 data transfer: asynchronous and isochronous. Asynchronous transport is the traditional computer memory-mapped, load and
store interface. Data requests are sent to a specific address and an acknowledgment is returned. In addition to an architecture that scales
with silicon technology, IEEE 1394 features a unique isochronous data channel interface. Isochronous data channels provide guaranteed
data transport at a pre-determined rate. This is especially important for time-critical multimedia data where just-in-time delivery eliminates
the need for costly buffering.
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The parity mode uses 1 parity bit for each byte, normally it is even parity mode, that is, each time the memory data is updated, parity bit will
be adjusted to have even count "1" for each byte. When next time, if memory is read with odd number of "1", the parity error is occurred
and this is called single bit error detection.
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