User guide

Features and Terms Reference

Multiprocessor Nios II Systems

The Nios II IDE is capable of running and debugging multiple Nios II processors

simultaneously. Altera hardware development tools automatically connect the JTAG debug

circuitry to the Nios II processor(s). Regardless of where the Nios II processor(s) reside in the

JTAG chain, the Nios II IDE can connect to each processor, download code, and run and

debug. For example, the Nios II IDE supports all of the following cases:

1 processor in an FPGA in a JTAG chain of 1 device—This is the simplest single-

processor case. This is the structure used on Nios development boards.

1 processor in an FPGA in a JTAG chain of 3 devices—This is a common case, in

which an Altera FPGA co-exists on a board with other devices in the JTAG test chain.

2 processors in an FPGA in a JTAG chain of 1 device—This is a common case for

multi-processor Nios II systems, in which multiple processors reside on a single FPGA.

2 processors, 1 each in 2 FPGAs in a JTAG chain of 2 devices

2 processors in separate FPGAs in separate JTAG chains—The two Nios II

processor systems can be on one board, or they can be in entirely separate systems.

This case requires multiple download cables to connect to the separate JTAG chains.

Multiprocessor systems require extra consideration during both hardware and software

development. If multiple processors exist in a single SOPC Builder system, the hardware

designer must consider which memory device(s) to share between the processors.

Furthermore, you must make sure that one processor doesn't store data in the same memory

space that another processor uses for code.