User guide

Features and Terms Reference

The ISS does not support reading or writing tightly coupled memories connected to

the Nios II processor.

The ISS does not support custom instructions.

The ISS models the Nios II ienable register as a complete 32-bit register. In

hardware (both on a target board and in HDL simulation), all bits associated with

unused interrupt inputs are always zero.

The EPCS Serial Flash Controller core only supports boot-from-flash behavior. If the

SOPC Builder system contains an EPCS Serial Flash Controller core, the simulation

does not model the full behavior of the EPCS device. The ISS only models the first 1

Kbytes of the controller's register map as a block of ROM. In the case that the

processor resets to the EPCS controller address (the typical boot-from-flash scenario),

the simulation relies on the fact that RAMs are pre-initialized. Therefore, the

controller's boot-loader does not need to copy code from EPCS memory to RAM.

Instead, the controller simply jumps directly to RAM.

You can run or debug on the ISS

from the Nios II IDE or from the Nios II Command Shell

command line, although Altera recommends command-line usage only to advanced users.