User`s guide

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Open
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M. PBSRAM is often used on L2 (level 2) cache of Socket 7 CPU. Slot 1 and
ocket 370 CPU do not need PBSRAM.
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For Socket 7 CPU, one burst data read requires four QWord (Quad-word, 4x16 = 64 bits). PBSRAM
only needs one address decoding time and automatically sends the remaining QWords to CPU
according to a predefined sequence. Normally, it is 3-1-1-1, total 6 clocks, which is faster than
asynchronous SRA
S
SDRAM DIMM that supports 100MHz CPU FSB bus clock.
PC133 DIMM
PC133 DIMM
DRAMS DIMM that supports 133MHz CPU FSB bus clock.