User`s guide

B-1
AP5T/AX5T Special Test Notice
Please refer to following FAQ (Frequently Asked Question) for the special test notice and interesting
features of INTEL TX chipset.
1. TX memory performance.
2. TX DMA/33 performance.
3. SDRAM that can be used.
4. 75/83.3MHz external clock.
5. ACPI new features. (Modem ring-on, OnNow, Suspend to HDD)
6. P55C MMX
7. FCC DoC
Note: FAQ may be updated without notice. If
you cannot find the information that you need in
this appendix, visit our WWW home page,
(address: http://www.aopen.com.tw) and check
the FAQ area and other new information.
Q: What is MMX?
A: MMX is the new single-line multiple-instruction technology of the new Intel Pentium PP/MT (P55C)
CPU. A new Pentium Pro CPU (Klamath) with MMX technology is also expected to be released soon.
The MMX instructions are specifically useful for multimedia applications (such as 3D video, 3D
sound, video conference). The performance can be improved if applications use these instructions. All
AOpen MBs have at least dual power onboard to support PP/MT. It is not necessary to have special
chipset for MMX CPU.
Q: What is PBSRAM (Pipelined Burst SRAM)?
A: For Pentium CPU, the Burst means reading four QWord (Quad-word, 4x16 = 64 bits) continuously
with only the first address decoded by SRAM. The PBSRAM will automatically send the remaining
three QWord to CPU according to predefined sequence. The normal address decoding time for
SRAM is 2 to 3 clocks. This makes the CPU data read timing of four QWord to be at least 3-2-2-2
and a total of 9 clocks if traditional asynchronous SRAM is used. However, with PBSRAM, there is
no need to decode address for rest three Qword. Therefore, data read timing can be 3-1-1-1, that is
equivalent to 6 clocks and is faster than asynchronous SRAM.
Q: What is EDO (Extended Data Output) memory?
A: The EDO DRAM technology of EDO is actually very similar to FPM (Fast Page Mode). Unlike
traditional FPM that tri-states the memory output data to start the pre-charge activity, EDO DRAM
holds the memory data valid until the next memory access cycle, that is similar to pipeline effect and
reduces one clock state.
Q: What is SDRAM (Synchronous DRAM)?
A: The SDRAM is a new generation DRAM technology that allows DRAM to use the same clock as the
CPU host bus (EDO and FPM are asynchronous and do not have clock signal). The idea is the same

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