User Guide

AWARD BIOS
3-13
Chipset Features Æ CPU to PCI Write Buffer
CPU to PCI Write
Buffer
Enabled
Disabled
This item is used to enable or disable CPU to PCI
write buffer.
Chipset Features Æ PCI Dynamic Bursting
PCI Dynamic
Bursting
Enabled
Disabled
This item is used to enable or disable PCI dynamic
bursting.
Chipset Features Æ PCI Master 0 WS Write
PCI Master 0 WS
Write
Enabled
Disabled
This item is used to control the PCI master write cycle.
If enabled, there is no wait state. If disabled, there will
be one wait state for PCI master write.
Chipset Features Æ PCI Delay Transaction
PCI Delay
Transaction
Enabled
Disabled
This item lets you control the Delayed Transaction
function of the VIA 586A chipset (Intel PCI to ISA
bridge). This function is used to meet latency of PCI
cycles to or from ISA bus. Try to enable or disable it, if
you have ISA card compatibility problem.
Chipset Features Æ PCI Master Read Prefetch
PCI Master Read
Prefetch
Enabled
Disabled
This item is used to control PCI master read prefetch.
If enabled, chipset will do prefetch only if enhanced
command. If disabled, it will be always prefetch.
Chipset Features Æ PCI#2 Access #1 Retry
PCI#2 Access #1
Retry
Enabled
Disabled
This item is used to enable or disable AGP master
retry disconnect. If enabled, AGP master will be
disconnected if max retries are attempted without
success. PCI#2 means AGP.