User Guide

AMI BIOS Utility
3-14
TURBO READ LEAD OFF
When enabled, BIOS skips the first input register in the DRAM when reading
data and therefore, speeds up the data read timings. Disable the option to
bypass the feature.
DRAM READ BURST TIMING
This parameter sets the timing for burst mode reads from DRAM. Everytime
the CPU reads the second-level cache miss, it reads four continuous memory
cycles on four continuous addresses from the DRAM.
The available parameter settings are X-4-4-4, X-3-3-3, and X-2-
2-2. Faster DRAMs require shorter wait states. The value of X depends on
the DRAM Lead-off Timing parameter setting. The default is X-4-4-4.
DRAM WRITE BURST TIMING
This parameter sets the timing for burst mode writes to DRAM. DRAM burst
write requests are generated by the CPU in four continuous addresses.
The available parameter settings are X-4-4-4, X-3-3-3, and X-2-
2-2. Faster DRAMs require shorter wait states. The value of X depends on
the DRAM Lead-off Timing parameter setting.
FAST RAS TO CAS DELAY (CLOCKS)
This option specifies the wait state between the row address strobe (RAS) and
column address strobe (CAS) signals. The available settings are 3 and 2.
DRAM LEAD-OFF TIMING (DLT)
This option specifies the lead-off time before data can be accessed. Some
DRAMs may require a longer delay to access data.
SPECULATIVE LEAD OFF
Enable the parameter to speed up the data read action by presenting the
DRAM controller read request before the controller chip decodes the data to
the final memory target (i.e., cache, DRAM or PCI).
TURN AROUND INSERTION
Enabling this option allows the CPU to insert one turn-around clock cycle to
the MD signals after asserting the MWE signal before enabling the MD
buffers. Set this to Disabled to select the back-to-back DRAM cycles for
asserting MWE signal.