Specifications
Table Of Contents
- AX45-8X Max
- What¡¦s in this manual
- You Must Notice
- Before You Start
- Overview
- Feature Highlight
- CPU
- Chipset
- Expansion Slots
- Memory
- Watch Dog Timer
- 1MHz Stepping Frequency Adjustment
- Ultra DMA 33/66/100/133 Bus Mater IDE
- On-board AC¡¦97 Sound
- Six USB2.0 Ports
- Dr. LED (Upgrade Optional)
- AGP Protection Technology
- Dr. Voice
- S/PDIF Connectors
- On-board IEEE 1394 Connectors
- Power Management/Plug and Play
- Hardware Monitoring Management
- Enhanced ACPI
- Super Multi-I/O
- Quick Installation Procedure
- Motherboard Map
- Block Diagram
- Hardware Installation
- About ¡§User Upgrade Optional¡¨ and ¡§Manufacture Upgrade Optional
- JP14 Clear CMOS Data
- CPU Installation
- CPU Jumper-less Design
- Full-range Adjustable CPU Core Voltage
- CPU and System Fan Connector (with H/W Monitoring)
- JP27 / JP28 Keyboard/Mouse Wake-up Jumper
- DIMM Sockets
- DDR 266(PC2100) and DDR 333(PC2700)
- JP29 DDR Voltage Jumper
- Front Panel Connector
- ATX Power Connector
- AC Power Auto Recovery
- STBY LED
- IDE and Floppy Connector
- ATA/133 Supported
- IrDA Connector
- Support AGP 8X (Accelerated Graphic Port) Expansion Slot
- AGP Protection Technology and AGP LED
- WOM (Zero Voltage Wake on Modem) Connector
- WOM by External BOX Modem
- WOM by Internal Modem Card
- WOL (Wake on LAN) Connector
- Support 10/100 Mbps LAN onboard
- CNR (Communication and Network Riser) Expansion Slot
- Colored Back Panel
- Support 2nd USB 2.0 Port
- Onboard IEEE 1394 Connectors
- Chassis Intrusion Connector
- CD Audio Connector
- AUX-IN Connector
- Game Port Bracket Supported
- Front Audio Connector
- S/PDIF (Sony/Philips Digital Interface) Connector
- Super 5.1 Channel Audio Effect
- Dr. LED Connector (User Upgrade Optional)
- JP15/JP16 Dr. Voice Language Select Jumpers
- JP1 Buzzer and JP2 Speaker Enable/Disable Jumpers
- Battery-less and Long Life Design
- Over-current Protection
- Hardware Monitoring
- Resettable Fuse
- 3300£gF Low ESR Capacitor
- Layout (Frequency Isolation Wall)
- Enlarged Aluminum Heatsink
- Vivid BIOS technology
- Driver and Utility
- AWARD BIOS
- Overclocking
- Glossary
- AC97
- ACPI (Advanced Configuration & Power Interface)
- AGP (Accelerated Graphic Port)
- AMR (Audio/Modem Riser)
- AOpen Bonus Pack CD
- APM (Advanced Power Management)
- ATA (AT Attachment)
- ATA/66
- ATA/100
- ATA/133
- BIOS (Basic Input/Output System)
- Bus Master IDE (DMA mode)
- CNR (Communication and Networking Riser)
- CODEC (Coding and Decoding)
- DDR (Double Data Rated) SDRAM
- DIMM (Dual In Line Memory Module)
- DMA (Direct Memory Access)
- ECC (Error Checking and Correction)
- EDO (Extended Data Output) Memory
- EEPROM (Electronic Erasable Programmable ROM)
- EPROM (Erasable Programmable ROM)
- EV6 Bus
- FCC DoC (Declaration of Conformity)
- FC-PGA (Flip Chip-Pin Grid Array)
- Flash ROM
- FSB (Front Side Bus) Clock
- I2C Bus
- IEEE 1394
- Parity Bit
- PBSRAM (Pipelined Burst SRAM)
- PC-100 DIMM
- PC-133 DIMM
- PC-1600, PC-2100 or PC-2700 DDR DRAM
- PCI (Peripheral Component Interface) Bus
- PDF Format
- PnP (Plug and Play)
- POST (Power-On Self Test)
- RDRAM (Rambus DRAM)
- RIMM (Rambus Inline Memory Module)
- SDRAM (Synchronous DRAM)
- Shadow E2PROM
- SIMM (Single In Line Memory Module)
- SMBus (System Management Bus)
- SPD (Serial Presence Detect)
- Ultra DMA
- USB (Universal Serial Bus)
- USB2.0 (Universal Serial Bus)
- VCM (Virtual Channel Memory)
- ZIP file
- Troubleshooting
- Technical Support
- Product Registration
- How to Contact Us

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CPU
Supports Intel
®
Socket 478 Pentium
®
4 (Willamette / Northwood) 1.4GHz~2.4GHz+ with 533MHz Front Side Bus (FSB) designed for Socket
478 technology.
Chipset
The motherboard is equipped with SIS 648 chipset. SIS 648 Host & Memory & AGP Controller integrates a high performance host interface
for Intel Pentium 4 processor, a high performance memory controller, a AGP interface. The SIS 648 Host Interface supports Intel Pentium
4 Series processors with FSB up to 133MHz. The host interface plays the role of processor transactions’ dispatcher. It dispatches
transactions to Memory, I/O interface and AGP bus. Transactions to different destinations can be dispatched concurrently in order to
maximum pipeline efficiency. The Memory controller can support DDR SDRAM. The memory controller also supports the Suspend to
RAM function by retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The AGP interface can
support external AGP slot with AGP 4X/8X capability and Fast Write Transactions.