System information

AMI BIOS
3-16
Chipset --> Speculative Leadoff
Speculative
Leadoff
Disabled
Enabled
Enable this item reduce one clock of DRAM read leadoff
timing by presenting the DRAM read request before the
controller chip decodes the final memory target (i.e., cache,
DRAM or PCI). For example, the DRAM read timing of 60ns
EDO is 6-2-2-2, Enable this option improve DRAM read
timing to 5-2-2-2.
Chipset --> Turn-Around Insertion
Turn-Around
Insertion
Disabled
Enabled
Enabling this option allows the chipset to insert one turn-
around clock cycle to the memory data bus for back-to-back
memory read and write cycles. If you have large loading on
the memory data bus, for example, four SIMMs with many
DRAM chips on the SIMM, this option provides a safety time
for data bus to switch direction.
Chipset --> Peer Concurrency
Peer
Concurrency
Disabled
Enabled
Peer Concurrency enables the CPU to run DRAM or cache
cycle while PCI master is accessing PCI target (slave),
however, the CPU to/from PCI bus will still be blocked. If
Disabled, the CPU will always be blocked when PCI master
owns the PCI bus. This function is useful if you have heavy
loading PCI masters on your system (such as PCI SCSI or
Network card).
Chipset --> Memory Error Check Mode
Memory Error
Check Mode
Disabled
Parity
ECC
This item selects the memory error check mode. The parity
mode uses 1 parity bit for each byte, each time the memory
data is updated, parity bit will be adjusted to have even
count "1" for each byte. When next time, if memory is read
with old number of "1", the parity error is occurred and this
is called single bit error detection. The ECC mode needs 8
ECC bit for 64 bit data, ECC bits are updated and checked
by special algorithm, the ECC algorithm has the ability to
detect double bit error and automatically correct single bit
error.