System information

AMI BIOS
3-15
Chipset --> DRAM Read Burst Timing
DRAM Read
Burst Timing
x444
x333
The Read Burst means to read four continuous memory
cycles on four predefined addresses from the DRAM. The
default value of 60ns FPM (Fast Page Mode) DRAM is x333
which means the 2nd,3rd and 4th memory cycles are 3 CPU
clocks. For EDO DRAM, the chipset will automatically
reduce one clock, that is, x444 becomes x333 and x333
becomes x222. The value of x is the timing of first memory
cycle and depends on the "DRAM Leadoff Timing" setting
Chipset --> DRAM Write Burst Timing
DRAM Write
Burst Timing
x444
x333
x222
The Write Burst means to write four continuous memory
cycles on four predefined addresses to the DRAM. This item
sets the DRAM write timing of the 2nd,3rd and 4th memory
cycles. There is no difference of EDO and FPM DRAM on
the write burst timing. The value of x depends on the "DRAM
Leadoff Timing" setting
Chipset --> Fast RAS to CAS Delay (clocks)
Fast RAS to
CAS Delay
(clocks)
3
2
This option specifies the wait state between the DRAM row
address strobe (RAS) and column address strobe (CAS)
signals. The default setting is 3 clocks.
Chipset --> DRAM Leadoff Timing
DRAM Leadoff
Timing
7/6/3/4
6/5/3/4
7/6/4/5
6/5/4/5
The Leadoff means the timing of first memory cycle in the
burst read or write. Actually, this setting includes not only
read/write leadoff timing but also the clocks of RAS
precharge and width of refresh RAS signal. The four digital
represent Read Leadoff/ Write Leadoff/ RAS Precharge/
Refresh RAS Width. For example, default is 6/5/3/4, which
means you have 6xxx DRAM read and 5xxx DRAM write,
with 3 clocks RAS precharge and 4 clock refresh RAS width.