System information

AMI BIOS
3-14
Warning: The default memory timing setting is
60ns to get the optimal performance. Because
the specification limitation of chipset, 70ns
SIMM can only be used with CPU external
clock 60MHz or below. To use 70ns SIMM
with 66MHz CPU external clock may result in
unstable system behavior.
Chipset --> DRAM Refresh Rate
DRAM Refresh
Rate
50 Mhz
60 Mhz
66 Mhz
This option lets you specify the clock frequency at which the
chipset refreshes the DRAM to avoid data lost. The setting
is normally equal to CPU bus clock (external clock).
Chipset --> ISA Clock
ISA Clock
PCICLK/4
PCICLK/3
This option specifies the ISA bus clock frequency. The
selections are PCI bus clock divide by 4 or PCI clock divide
by 3, PCI clock is the half of CPU bus clock, for example,
66Mhz CPU bus clock has 33Mhz PCI bus clock, and the
ISA bus clock should be 33M/4= 8.25Mhz, The ISA bus
clock must be near 8Mhz.
Chipset --> Turbo Read Leadoff
Turbo Read
Leadoff
Disabled
Enabled
This item is reserved for cacheless configuration only. When
enabled, chipset bypasses the first data input of the DRAM
data pipeline buffer. Therefore, reduces one clock of DRAM
read leadoff timing. The default is Disabled.
Warring: "Turbo Read Leadoff" can only be
enabled for cacheless system or external cache
disabled.