Specifications

M
M
K
K
7
7
3
3
L
L
E
E
-
-
N
N
/
/
M
M
K
K
7
7
3
3
L
L
E
E
-
-
V
V
O
O
n
n
l
l
i
i
n
n
e
e
M
M
a
a
n
n
u
u
a
a
l
l
P
P
B
B
S
S
R
R
A
A
M
M
(
(
P
P
i
i
p
p
e
e
l
l
i
i
n
n
e
e
d
d
B
B
u
u
r
r
s
s
t
t
S
S
R
R
A
A
M
M
)
)
For Socket 7 CPU, one burst data read requires four QWord (Quad-word, 4x16 = 64 bits). PBSRAM only needs one address
decoding time and automatically sends the remaining QWords to CPU according to a predefined sequence. Normally, it is
3-1-1-1, total 6 clocks, which is faster than asynchronous SRAM. PBSRAM is often used on L2 (level 2) cache of Socket 7 CPU.
Slot 1 and Socket 370 CPU do not need PBSRAM.
P
P
C
C
-
-
1
1
0
0
0
0
D
D
I
I
M
M
M
M
SDRAM DIMM that supports 100MHz CPU FSB bus clock.
P
P
C
C
-
-
1
1
3
3
3
3
D
D
I
I
M
M
M
M
SDRAM DIMM that supports 133MHz CPU FSB bus clock.
P
P
C
C
I
I
(
(
P
P
e
e
r
r
i
i
p
p
h
h
e
e
r
r
a
a
l
l
C
C
o
o
m
m
p
p
o
o
n
n
e
e
n
n
t
t
I
I
n
n
t
t
e
e
r
r
f
f
a
a
c
c
e
e
)
)
B
B
u
u
s
s
Bus for the internal connection of peripheral devices, high-speed data channel between the computer and expansion card.
P
P
D
D
F
F
F
F
o
o
r
r
m
m
a
a
t
t
98
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