Specifications

2-26 MS462XX MM
RECEIVER MODULE BLOCK DIAGRAMS THEORY OF OPERATION
24
25
22
13
11
109
87
6
5 3
1
2
TO FRONT
PANEL BOARD
(D43018)
MAIN CPU:
1 - MC68040 CPU
2 - DRAM CONTROLLER
3 - 16 MB LOCAL DRAM
4-48MBEXP.DRAM
5 - 4 MB NON-VOL SRAM
6 - 3V LITHIUM BATTERY
7-CSPLD
8 - SCSI CONTROLER (OPT.)
9 - INTERRUPT CONTROLLER
10 - LAN CONTROLLER
11 - PERIPHERAL BUS SIZER
12 - 10 MB FLASH
13 - OPTION/MODEL SWITCHES
14 - BOOT EPROM
15 - MASTER/SLAVE GPIB CTRLS
16 - KEYBOARD CTRL
17 - FLOPPY DISK CTRL
18 - STATE MACHINE
19 - SERIAL PORT CTRL
DSP CORE:
20 - TMS320C44 DSP
21 - 2 MB LOCAL SRAM
22 - 512 KB LOCAL EPROM
23 - 128 KB GLOBAL SRAM
24 - DSP PLD
25 - DSP COMM ADC PLD
GRAPHICS CORE:
30 - TMS34020 GRAPHICS PROC.
31 - 1 MB DRAM
32 - 1 MB LOCAL VRAM
33 - PALETTE
34 - GSP PLD
35 - LCD PLD
4
20
30
12
21
23
31
32
33
34
35
14
15
16
17
18
19
TO LCD
BKLGHT
TO LCD
FLEX CABLE
(D43020)
TO SYSTEM
MOTHERBOARD
TO CONNECTOR
BOARD (D43017)
Figure 2-1. CPU Module Block Diagram