Specifications

2-7 CENTRAL

PROCESSOR

MODULE

The Central Processor Module (Figure 2-1, following page) contains most

of the digital functionality of the MS462XX, and consists of three major

sections, each of which contains its own processor:

Main CPU

DSP Core

Graphics Core

The Main CPU section is a MC68040 with a primary cache and includes a

local system memory (16 MB Fast Page Mode DRAM upgradable to

64 MB, 4 MB Battery Backed SRAM, 10 MB Flash, 512 KB Boot EPROM,

128 KB NVRAM), Ethernet interface, GPIB master/slave interfaces, par

allel printer port, 2 serial ports, interfaces to the front panel keypad, front

panel floppy disk drive, an external keyboard, and an interface to the ex

ternal SCSI-2 drive.

The DSP core is for calculating the sweeping S-parameter measurements

and includes the TMS320C44 DSP, local system memory (2 MB SRAM,

32 KB Boot EPROM), global system memory (128 KB SRAM) used as

dual access memory to the 68040 CPU, and an interface to the A/D con-

verters located on the Receiver Module.

The BBRAM chip has a rated life span of 10-years, and the SRAM backup

battery has a worst-case life span of 2-years at 25°C when the instrument

is stored (always off). Exposure to temperatures above 60°C will

dramtically reduce this worst-case life span. The SRAM backup battery

should be replaced every three years.

The Graphics core is for driving the front panel color LCD and external

VGA monitor with the instrument display measurements, and it includes

the TMS34020 graphics processor, local system memory (1 MB DRAM,

1 MB Video RAM), a video palette, drivers for the VGA interface, an LCD

controller, and an interface to the color LCD module through the Flex Ca

ble (part number D43020).

All the signals that go on or off the board go to one of three destinations.

They can be described as connections that go to the rear panel, the front

panel, or the system motherboard. Only the rear panel connections are di

rectly accessible.

2-8 RECEIVER

MODULE BLOCK

DIAGRAMS

There are 20 different configurations of receiver modules, based on model

and option number. Block diagrams of these configurations are shown in

the foldout Figures 2-2 through 2-22, on the following pages.

THEORY OF OPERATION CENTRAL PROCESSOR MODULE

MS462XX MM 2-25