Specifications
Current draw is minimal on the board (<100 mA at +5 volts, a few hun
-
dred mA on ±12 volts) so three port regulators are used. A low dropout
regulator is used for the +5V supply.
The digital section employs two addresses only. Latches provide access to
the 16-bit data bus for address 0, which controls everything except the
analog monitor. Another latch, address 1, provides access to the data bus
for the analog monitor.
The input and output of the two receiver sections is shared (since the In
-
termediate Frequency ports are shared). The front-end consists of a
switched attenuator (0 and 25 dB) and a switched gain amplifier (10, 20
and 30 dB gain). These are primarily used by the noise figure receiver but
will be used by group delay for extended gain ranging.
An analog monitor section allows system monitoring of several key power
supply voltages, the lock status of the frequency translation group delay
synthesizer, and the board revision. This is used during self test.
Frequency
Translating Group
Delay (FTGD)
Synthesizer
The FTGD synthesizer circuit is used to generate the 453.125 kHz
modulating signal for the frequency translating group delay
measurements. The purity requirements are < 40 dBc harmonics and the
frequency accuracy requirements are ± 1 Hz. The signal is generated with
a simple PLL with a single pole loop filter and a synthesizer VCO.
The signal is filtered with a ceramic element and split providing refer-
ence signals that go to the Mod input, J5 on the Source and REF IF input
and J17 on the Receiver assembly. The output amplitude is adjusted
based on the band of the source. This is required to maintain a
modulation index with frequency and is accomplished with a simple
4-state voltage divider. The main source mod drive is summed into the
main source tune line within the Source Module.
Source Range
(MHz)
State
Relative to Through Band
Normalized Modulation
Signal Amp
10-400 heterodyned 1
400-800 divided 2
800-1600 through band 1
1600-3200 doubled 0.5
3200-6000 doubled twice 0.25
The 10 MHz reference input is shaped and level shifted to minimize prob
-
lems at the first divider stage. The logic families within the loop are quite
mixed based on current technology.
The 453.125 kHz modulation frequency is chosen to match a valid under
sampled Intermediate Frequency of the Analog to Digital system. It is
sufficiently high to allow reasonable group delay resolution and requires
no additional down conversions for detection.
2-22 MS462XX MM
OPTION MODULES THEORY OF OPERATION