Specifications

ADC Clock
Generation/ DSP
Communication
Port Interface
The ADC requires specific clock pulses to convert the signal, and it’s very
sensitive to these pulses. To generate the clock signals required for cor
-
rect operation, a state machine was designed in the PLD. The PLD state
machine takes the system 10 MHz clock as an input, and generates the
ADC clocks as outputs. The ADC requires a start conversion pulse, the
CCMD signal at the sampling frequency (156.25 kHz), along with subse
-
quent bit conversion clock pulses at the bit output frequency. The bit out
-
put frequency is approximately 3.33 MHz. The EXT_CLK is the bit con
-
version clock. The A/D bits are sent out through the backplane to the
DSP COMM PLD on the microprocessor board. To clock the bits into the
DSP COMM PLD, the BIT_CLK signal is used. The DSP requires four
separate bytes to be clocked into its communication port to form a 32-bit
word. Since the ADC on the receiver board only generates 18 serial bits,
the DSP COMM PLD shifts these bits into byte words and clocks the
bytes into the DSP communication port. A dummy byte is clocked into the
DSP to complete the 32-bit word.
10 MHz Clock
Distribution
The 10 MHz system time base resides on the receiver board. An external
10 MHz clock can be switched in via J16 using the EXT_10MHZ bit. The
10 MHz time base is used on the receiver board to generate the ADC
clocks, and it is also routed to the Source Module via J13, the Optional
Source Module via J14, and the Options Board via J15.
RF Component
Control
Mounted on the receiver board are the RF signal separation components.
Depending on the system configuration, these include:
q
Port modules
q
Auto-Reversing Module (MS462XB/C/D only)
q
Non-Reversing Module (MS462XA only)
q
Primary and Secondary Source Switched Doubler Module
q
Primary and Secondary Source Switched Tripler Module
q
Port 1 and Port 3 Step Attenuators
q
Port 3 Module (MS462XB and MS462XC only)
q
Port 1 and Port 2 Switch Modules
q
High Isolation Switch Module (MS462XD only)
The receiver board PLD controls these components via 14-pin ribbon con
-
nectors (10 pin for the Step Attenuators). Dual peripheral drivers control
the Step Attenuators. DC bias can be supplied through the rear panel
BNC connectors (J26, J27) to the Port Modules via 3-pin Berg connectors
on the PCB Assy. Bias current is fused at 0.5 amp and bias switching is
provided by a relay controlled by a driver IC.
2-14 MS462XX MM
RECEIVER MODULE THEORY OF OPERATION