Specifications
Test Channel
Intermediate
Frequency Path
The purpose of the Test Channel I.F. circuitry is to amplify, filter, and
sample the test channel signal after it has been down converted to a fixed
intermediate frequency. Sampling is performed by an18-bit ADC at the
fixed sampling rate of 156.25 samples/second. Amplification is necessary
to optimally position the test signal within the input signal range of the
ADC. Filtering is performed to prevent aliasing of noise onto the desired
signal that occurs through the sampling process.
There are three different types of signals that are sent as inputs to the
I.F. chain:
q
125 kHz sinusoid
q
453.125 kHz sinusoid
q
DC signal
The origin and subsequent processing of these signals is discussed below.
In S-Parameter operation, a 10 MHz to 6 GHz sinusoid is sent out one of
the front panel ports, appropriately channeled to the down converter, and
converted to a fixed 125 kHz sinusoid. This signal is cabled to the front
end of the Test Channel I.F. chain (J21) through an MCX connector. An
RC lowpass filter with a cutoff of 160 kHz follows the input switch to pre-
vent RF feed through signals from reaching the input amplifier.
If the instrument is reversing, the signal is routed directly to the input
amplifier and the gain of the following amplifier is 20 dB. If the instru-
ment is non-reversing, the signal is routed through a 10 dB attenuator
before the input amplifier and the gain of the following amplifier is 15 dB,
controlled by the TEST_GAIN bit. This gain is appropriately set upon in-
strument power-up, after which it remains constant while the instrument
is in use.
After the input amplifier, the signal is filtered by a fifth order elliptical
lowpass filter with a cutoff of approximately 125 kHz. This amplifier pro
-
vides 30 dB of switched gain, controlled by the T_GR1 bit, so that low
level signals can be amplified to a more optimal ADC range. This process
of gain ranging is done by detecting the signal level, determining if it is
low enough for 30 dB of extra gain, applying the gain if necessary, then
remeasuring the signal.
When the extra 30 dB of gain is used, software division by this gain factor
is subsequently performed so that a linear transfer function is obtained.
A switched attenuator follows the second amplifier for the purpose of re
-
moving gain if the input signal level is too high. After the switched at
-
tenuator, a second order Chebyshev active highpass filter filters the sig
-
nal before it is sampled by the ADC. The overall cascade of the elliptical
lowpass filter and the Chebyshev highpass forms the bandpass filter re
-
quired for under sampling.
In the frequency translation group delay mode, a 453.125 kHz sinusoid is
switched in on J20 from the options board. The switching is controlled by
the direct in bit, and is done at the high impedance node of the ADC
buffer amplifier. Sampling of this signal is done at the same 156.25 kHz
rate, and this under sampling results in 10 samples of a 15.625 kHz
THEORY OF OPERATION RECEIVER MODULE
MS462XX MM 2-11