Specifications

2-4 RECEIVER MODULE The Receiver module is made up of the RF components that are used to
configure the system for the various options. This encompases the fre
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quency translation module, which produces the 125 kHz Intermediate
Frequency, the Test and Reference channel Intermediate Frequency
paths, the system 10 MHz time base, and the circuitry for the control of
the RF components. At the end of the Intermediate Frequency paths, the
signal to be measured is sampled and sent to the Central Processor Mod
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ule. This module has Digital Signal Processing (DSP) prior to processing
the numerical values into the CPU. Determination of magnitude and
phase for S-Parameter measurements is done by calculating a single fre
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quency Digital Fourier Transfer (DFT) of a coherently sampled Interme
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diate Frequency Signal. A Programmable Logic Device (PLD) accom
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plishes control of the receiver board and Analogue to Digital (ADC) clock
generation.
An intermediate frequency signal of 125 kHz was chosen because of the
division ratio to the 10 MHz reference combined with the optimized sam
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ple rates used in the analogue to digital conversions.
Down Conversion
Module
The Down Conversion Module (DCM) translates the Test Port and the
Reference Port signals down to the 125 kHz intermediate frequency sig-
nal.
The input at J5 takes the local oscillator signal from the Source Module.
The signal is split into two paths, one for the Test Port Mixer and the
other for the Reference Port Mixer. Two identical paths are used to pro-
vide the mixer local oscillator drive. The reason for the two paths is to
maintain good isolation between the two signal paths. After the power di-
vider, the local oscillator signal passes through a limiter that is used to
flatten the power level variations of the incoming local oscillator signal.
In so doing, it minimizes the AM to PM conversion in the local oscillator
path. The local oscillator signal is filtered to provide a clean signal for the
mixer. Built into the Down Conversion Module is a local oscillator doubler
(used in 6 GHz models) or a tripler (used in 9 GHz models).
The Test Port signal and the Reference Port signal go to J4 and J1,
respectively. The outputs from the mixers are fed through buffer amplifi
-
ers before going to the intermediate frequency amplifiers.
Digital Interface The Programmable Logic Device provides the main digital interface with
the microprocessor. The load pulse, board select 5, data bits D0-D11, and
address bits A0-A4 are inputs to this device that provide the address de
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coding and data latching. Latches are written to by setting the desired ad
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dress and data bits, then the strobing board selects 5 low. An additional
strobe, the load pulse, is used on certain latches as a final strobe when
pre-loading is performed. Note that every latch is a write latch and every
latch uses board select 5 for strobing.
2-10 MS462XX MM
RECEIVER MODULE THEORY OF OPERATION