Specifications

ALC Circuitry The source side differs from the LO side primarily in its ability to have
controllable output power. The feedback from a level detector controls the
level of the source output. The level of the signal can be controlled over a
20 dB range. In the ALC circuitry, a DAC is set to a calibrated value for a
desired power level. The ALC loop then adjusts the level of the source
output until the detector output matches the reference voltage. A shaper
circuit compensates for the non-linear characteristics of the modulator
and doubler.
Once placed into a system, the Source/LO Module may be calibrated for
leveled power out of the port. In general, the Power Level DAC is stepped
while the Source is tuned to a fixed frequency. The port output level is
measured with a power meter. The power level at the port is dependent
not only on the source output power itself, but also upon the losses
through various components in the RF deck. The results are then used to
curve-fit an equation that relates DAC values to port power. Fora3GHz
system, the measurements are performed at 1 GHz. If the system is a
6 GHz unit, the measurements are performed at both 1 GHz and 4 GHz.
The power curve did not change much with frequency, only the offsets.
Therefore, the same curve-fit equations could be used with a correction
for the different offsets at various frequencies. The curve-fit equation cal-
culated using 1 GHz data is applied for system frequencies less than
3 GHz. The 4 GHz curve-fit equation is used in the doubler band (i.e. fre-
quencies greater than 3 GHz). The power DAC is set to a 0 dBm port
power using the appropriate curve-fit equation, then the resulting error
offset is measured. The offsets for different frequency steps are stored in
a table and intermediary frequencies are interpolated.
Additionally, a shaper DAC calibration is performed when the system is a
6 GHz unit. The shaper DAC is in place to help compensate for changes in
the doubler characteristics.
At band switch points, the source takes longer to settle. During the set
-
tling period, there is a lack of RF signal to the ALC detector diode, thus
the ALC circuitry will set the output power higher. Therefore, the ALC is
level-dipped at band switch points to prevent large power spikes from hit
-
ting the DUT during these transition periods. The level-dip is performed
by switching a fixed voltage into the loop.
Operation Modes There are two operation modes:
Common
Offset Mode
Traditionally, the source and LO output signals are generated
independently. An alternative mode of operation is possible
where the LO offset VCO also locks up the source loop. The
source offset VCO is disabled in this mode. The DDS outputs on
the two sections then make up the frequency difference between
the two outputs. Sharing a common offset VCO allows the two
signal sources to better track each other. The resulting IF has
better phase noise because much of the offset VCO noise is
ratioed out.
2-8 MS462XX MM
SOURCE MODULE THEORY OF OPERATION