Specifications

The loop amplifier has a gain of 4; therefore, the sensitivity at the PLL IC
output is very high. Thus, any noise injected at this point has noticeable
affects on the output noise characteristics.
DDS Reference
Clock
In order to generate accurate DDS frequencies, an accurate reference
clock must be provided to the two DDS ICs. The 32 bits of the DDS fre
-
quency register allow the minimum output resolution of F
clk
divided by
232. By phase locking the DDS reference clock VCXO to 26.8435456 MHz,
the resulting minimum resolution is 0.00625 Hz.
To get such a precision frequency from the VCXO, it is phase-locked to the
system’s 10 MHz reference. A third DDS IC, using the VCXO as its clock,
is programmed to output 100 kHz. The system reference is divided down
to 100 kHz and is compared against the DDS output. Only when the clock
is exactly 26.8435456 MHz will the programmed DDS produce a phase
locked 100 kHz.
The phase detector feeds back to the VCXO tuning line to precisely tune
the clock frequency.
Bounding Circuitry Bounding is a term for the circuitry that is used to ensure that the VCOs
are kept within their range and that the correct frequency is generated.
The mixing of the main and offset signals produces an additive as well as
the desired subtractive product. Therefore, there is the potential that the
main oscillator loops will try to lock on to the wrong signal. To prevent
locking on the wrong side, additional PLL ICs are wrapped around the
main loop phase detector as bounding circuits. The proper polarity in the
loop requires that the main oscillator always be lower in frequency than
the offset oscillator.
The upper bound PLL is programmed for the offset VCO frequency. When
the main VCO goes higher in frequency than the offset VCO, a correction
pulse is generated that is fed into the main oscillator loop. This magni
-
tude of the correction pulse is large enough to push the main VCO to the
correct side.
In addition to being prevented from swinging too high, the main VCO
must also be bounded on the low end. For lower main VCO frequencies,
the difference frequency increases. However, the mixer has a limited
bandwidth. When the bandwidth is exceeded, the output response drops
off and it will seem as if the main VCO is too high in frequency, instead of
too low. Once again, positive feedback would result. A lower bound PLL
will issue a correction pulse to push the main VCO higher in frequency
when the bound is exceeded.
Both the source and the LO sides incorporate bounding circuits. When the
main VCO is within an acceptable range, there is no contribution from
the bounding circuits. The PLL ICs used for the bounding circuits are the
same components used in the offset VCO loops.
2-6 MS462XX MM
SOURCE MODULE THEORY OF OPERATION