Specifications

The internal ALC level loop allows for a leveled range of –11 dBm to
+20 dBm out of the Source RF port.
The Local Oscillator is not used on the optional Source module. All fre
-
quency loops are phase locked to the internal 10 MHz reference oscillator
in the MS462XX.
NOTE
Six gigahertz instruments use a Switched Doubler module
immediately following the source(s). Nine gigahertz instru
-
ments use a Switched Tripler module immediately following
the source(s). The doublers or triplers are installed on the
Receiver PCB assembly.
Digital Interface All modules in the instrument share the same bus connections to the mi
-
croprocessor via the motherboard. The common data and address bus con
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sists of 16 data bits, 5 address lines, and 5 board select lines. Within the
Source/LO module, the incoming address and board select lines are de
-
coded to direct data between the common bus and internal module
latches. Transceivers are used to buffer the common data bus from an in-
ternal data bus. When a latch located on the module is addressed, the
transceivers will enable the transfer of data to or from the internal data
bus.
Main Oscillator
Loops
The Source and LO RF outputs are both generated by voltage controlled
oscillators (VCOs) that nominally cover 800 to 1600 MHz. The outputs of
the VCOs are processed to ultimately produce the final outputs of the
module. Additionally, the outputs of the main oscillators are sampled and
fed back, in order to be phase-locked to the system reference 10 MHz. The
phase locking circuitry for the Source and LO VCOs are essentially iden
-
tical in their implementation.
When phase locking the main oscillator, the VCO is mixed with an offset
oscillator to produce a lower frequency signal. This mixed down signal is
input to a phase detector and is compared to a signal produced by a Di
-
rect Digital Synthesis (DDS) IC. The DDS has better than 1 Hz resolu
-
tion, which is transferred to the main VCO. The phase detector output is
fed into a loop filter, which supplies the tuning voltage (0.5 to 20 volts) to
the VCO.
Offset Oscillator
Loops
The offset oscillator used by the source and the LO are also 800 to
1600 MHz VCOs. The VCOs are also phase-locked to the system’s 10 MHz
reference (f
ref
) using a PLL IC. The PLL IC integrates two programmable
dividers, a prescaler and a phase/frequency detector. The PLL IC operates
in frequency ranges up to 2.5 GHz. The circuitry used to lock up the
source offset oscillator is reproduced for the LO offset VCO.
The outputs of the two dividers are programmed to 625 kHz. The phase
detector issues a correction current pulse using the internal charge pump.
The loop amplifier integrates current pulses from the PLL IC. The tuning
sensitivity at the VCO input is approximately 50 MHz/V.
THEORY OF OPERATION SOURCE MODULE
MS462XX MM 2-5