User`s manual

Page 6 of 35 A2500R24x – User’s Manual
Release Date 09/05/12
1.3. Features
Features:
 Frequency range: 2400 – 2483.5 MHz
 Ultra small package size 9mm x 12mm
x 2.5mm
 Impedance controlled multi-layer PCB
 Shielded Package
 1.8 to 3.6 V operation
 SPI Interface
 RoHS Compliant
 Approximate weight 0.4 grams
 LGA Footprint
 Low Power Consumption
 Digital RSSI output
 Programmable channel filter bandwidth
 Programmable output power up to +1
dBm
 High sensitivity (–104 dBm at 2.4
kBaud, 1% packet error rate)
 Low current consumption (13.3 mA in
RX, 250 kBaud, input well above
sensitivity limit)
 Separate 64-byte RX and TX data
FIFOs
 Fast startup time: 250µs from SLEEP
to Rx or Tx mode
 Data Rate: 1.2 – 500 Kbit/Sec
 Programmable data rate from 1.2 to
500 kBaud
 Sleep state: 0.4µA
 Idle State: 1.5mA
Benefits Summary:
 Operating temperature -40 to +85C
 100% RF Tested in production
 Common footprint for all family
members
 No RF engineering experience
necessary
 Only requires a 2 layer PCB
implementation
 Excellent receiver selectivity and
blocking Performance
 Suitable for frequency hopping and
multichannel systems due to a fast
settling frequency synthesizer with 90
µs settling time
 FCC 15.247, IC RSS-210 and IC RSS-
Gen certified.
 Compliant with ETSI EN 300 328
 No regulatory “Intentional radiator”
testing required for integrating module
into end product. Simple certification
labeling replaces testing.
1.4. Theory of Operation
The A2500R24C and A2500R24A are for low power wireless applications in the 2400MHz to
2483.5MHz global ISM/SRD band. The devices can be used to implement a variety of networks,
including; point to point, point to multipoint, peer to peer and mesh networks.
The A2500R24C and A2500R24A both interface to an application microcontroller via an SPI
bus. Physical and MAC layer functionality are accessed via the SPI bus, through addressable
registers as well as execution commands. Data received or to be transmitted are also accessed
through the SPI bus and are implemented as a FIFO register (64 bytes each for Tx and Rx).
To transmit, a frame of data is placed in the FIFO; this may include a destination address. A
transmit command is given, which will transmit the data according to the initial setup of the