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Appendix B. I2C slave address formats

A standard I2C address is the first byte sent be the I2C master, whereas only the first seven bit form the

adress, the last bit (R/W-bit) defines the direction in which the data is sent. I2C has a 7-bit address space

and can address 112 slaves on a single bus (16 of the 128 addresses are reserved fo special purposes).

Figure B.1. Definition of a I2C slave address in 7-bit format

Each I2C-able IC has a determined bus address. The 4 upper bits of the bus address are called Device Type

Identifier and define the chip type. The lowest three bits called sub-address or Chip Enable Address are

usually defined by the corresponding wired control pins. So, in total up to 8 similar IC's can be used on

a single I2C bus.

Because of a lack of address space a 10-bit addressing mode was introduced later. This new mode is

downwards compatible to the 7-bit standard mode through usage of 4 of the 16 reserved addresses. Both

addressing modes can be used simultaneously, which implies that 1136 slaves can be used on a single bus.

Figure B.2. Definition of a I2C slave address in 10-bit format

Note

Devices of type AnaGate SPI and AnaGate Universal Programmer do support both

addressing modes in general. The I2CRead(3) and n>I2CWrite(3) functions address the

slaves via a two byte parameter.

Addressing of serial EEPROM

The device type identifier of a serial EEPROM is defined as 0xA. This results to the following schematic

structure of an address (the chip enable bits are often named E0, E1 and E2 in literature):

Table B.1. I2C EEPROM addressing examples

Device Type Identifier Chip Enable

R/W

b7 b6 b5 b4 b3 b2 b1 b0

EEPROM-

Memory

M24C01 1 0 1 0 E2 E1 E0 R/W 128 byte

M24C02 1 0 1 0 E2 E1 E0 R/W 256 byte

M24C04 1 0 1 0 E2 E1 A8 R/W 512 byte