- Analog Devices, Inc. Embedded Processor Specification Sheet
Rev. C | Page 6 of 48 | December 2006
ADSP-TS201S
33.6G bytes per second, enabling the core and I/O to access
eight 32-bit data-words and four 32-bit instructions each cycle.
The DSP’s flexible memory structure enables:
• DSP core and I/O accesses to different memory blocks in
the same cycle
• DSP core access to three memory blocks in parallel—one
instruction and two data accesses
• Programmable partitioning of program and data memory
• Program access of all memory as 32-, 64-, or 128-bit
words—16-bit words with the DAB
EXTERNAL PORT
(OFF-CHIP MEMORY/PERIPHERALS INTERFACE)
The ADSP-TS201S processor’s external port provides the DSP’s
interface to off-chip memory and peripherals. The 4G word
address space is included in the DSP’s unified address space.
The separate on-chip buses—four 128-bit data buses and four
32-bit address buses—are multiplexed at the SOC interface and
transferred to the external port over the SOC bus to create an
external system bus transaction. The external system bus pro-
vides a single 64-bit data bus and a single 32-bit address bus.
The external port supports data transfer rates of 1G byte per
second over the external bus.
The external bus can be configured for 32-bit or 64-bit, little-
endian operations. When the system bus is configured for 64-bit
operations, the lower 32 bits of the external data bus connect to
even addresses, and the upper 32 bits connect to odd addresses.
The external port supports pipelined, slow, and SDRAM proto-
cols. Addressing of external memory devices and memory-
mapped peripherals is facilitated by on-chip decoding of high
order address lines to generate memory bank select signals.
Figure 3. ADSP-TS201S Memory Map
RESERV ED
RE SER V ED
INTERNAL REGISTERS (UREGS)
INTERNAL ME MORY BLOCK 4
I NTE RNAL MEM ORY BLOCK 2
I NTE RNAL MEM ORY BLOCK 0
0x03FFFFFF
0x001E0000
0x 001 E03FF
0x000DFFFF
0x 00 0C0 000
0x0009FFFF
0x0 00 8000 0
0x0005FFFF
0x0 00 4000 0
0x0001FFFF
0x0 00 0000 0
INTERNAL SPACE
PROCESSOR I D 7
PROCESSOR I D 6
PROCESSOR I D 5
PROCESSOR I D 4
PROCESSOR I D 3
PROCESSOR I D 2
PROCESSOR I D 1
PROCESSOR I D 0
BROADCAST
HOS T (MSH)
BANK 1 (MS 1)
BANK 0 (MS 0)
MSSD BANK 0 (MSSD0)
INTERNAL MEM ORY
0x 50 0000 00
0x4 00 0000 0
0x 38 0000 00
0x 300 0000 0
0x 2C00 0000
0x 280 0000 0
0x 240 0000 0
0x 200 0000 0
0x 1C00 0000
0x 180 0000 0
0x 140 0000 0
0x 100 0000 0
0x 0C00 0000
0x 03 FF FFFF
0x 000 0000 0
GLOBAL SPACE
0 xFFFFFFFF
M
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EACH IS A COPY
OF INTERNAL SPACE
RESERV ED
INTERNAL ME MORY BLOCK 6
INTERNAL MEMORY BLOCK 8
0x0011FFFF
0x0 01 0000 0
INTERNAL ME MORY BLOCK 1 0
0x0015FFFF
0x0 01 4000 0
RESERV ED
RESERV ED
RESERV ED
RESERV ED
RESERV ED
RESERV ED
SO C REGISTE RS (U RE GS)
0x001F0000
0x 00 1F0 3FF
MSSD BANK 1 (MSSD1)
MSSD BANK 2 (MSS D2 )
MSSD BANK 3 (MSSD3)
0x 60 0000 00
0x 70 0000 00
0x 80 0000 00
RESE R VED
RESE R VED
RESE R VED
RESE R VED
0x 54 00 00 00
0x4 40 00 00 0
0x 64 00 00 00
0x 74 00 00 00