Datasheet

SSM2603 Data Sheet
Rev. C | Page 6 of 32
Table 5. Digital Audio Interface Master Mode Timing
Limit
Parameter t
MIN
t
MAX
Unit Description
t
DST
30 ns PBDAT setup time to BCLK rising edge
t
DHT
10 ns PBDAT hold time to BCLK rising edge
t
DL
10 ns RECLRC/PBLRC propagation delay from BCLK falling edge
t
DDA
10 ns RECDAT propagation delay from BCLK falling edge
t
BCLKR
10 ns BCLK rising time (10 pF load)
t
BCLKF
10 ns BCLK falling time (10 pF load)
t
BCLKDS
45:55:00 55:45:00 BCLK duty cycle (normal and USB mode)
Figure 4. Digital Audio Interface Master Mode Timing
Table 6. Master Clock Timing
1
Limit
Parameter t
MIN
t
MAX
Unit Description
t
XTIY
54 ns MCLK/XTI clock cycle time
t
MCLKDS
40:60 60:40 MCLK/XTI duty cycle
t
XTIH
18 ns MCLK/XTI clock pulse width high
t
XTIL
18 ns MCLK/XTI clock pulse width low
t
COP
20 ns CLKOUT propagation delay from MCLK/XTI falling edge
t
COPDIV2
20 ns CLKODIV2 propagation delay from MCLK/XTI falling edge
1
CLKDIV2 bit (Register R8, Bit D6) is set to 0
Figure 5. System (MCLK) Clock Timing
07241-026
BCLK
PBLRC/
RECLRC
PBDAT
RECDAT
t
DDA
t
DST
t
DHT
t
DL
07241-035
t
COPDIV2
t
COP
MCLK/XTI
CLKOUT
CLKODIV2
t
XTIH
t
XTIL
t
XTIY