Datasheet

Data Sheet SSM2603
Rev. C | Page 29 of 32
ALC CONTROL 1, ADDRESS 0x10
Table 36. ALC Control 1 Register Bit Map
D8 D7 D6 D5 D4 D3 D2 D1 D0
ALCSEL[1:0]
MAXGAIN[2:0]
ALCL[3:0]
Table 37. Descriptions of ALC Control 1 Register Bits
Bit Name Description Settings
ALCSEL[1:0] ALC select 00 = ALC disabled (default)
01 = ALC enabled on right channel only
10 = ALC enabled on left channel only
11 = ALC enabled on both channels
MAXGAIN[2:0] PGA maximum gain 000 = −12 dB
001 = −6 dB
… In 6 dB steps
111 = 30 dB (default)
ALCL[3:0] ALC target level 0000 = −28.5 dBFS
0001 = −27 dBFS
… In 1.5 dBFS steps
1011 = −12 dBFS (default)
… In 1.5 dBFS steps
1111 = −6 dBFS
ALC CONTROL 2, ADDRESS 0x11
Table 38. ALC Control 2 Register Bit Map
D8 D7 D6 D5 D4 D3 D2 D1 D0
0 DCY[3:0] ATK[3:0]
Table 39. Descriptions of ALC Control 2 Register Bits
Bit Name Description Settings
DCY[3:0] Decay (release) time control 0000 = 24 ms
0001 = 48 ms
0010 = 96 ms
0011 = 192 ms (default)
… (Time doubles with every step)
1010 = 24.576 sec
ATK[3:0] ALC attack time control 0000 = 6 ms
0001 = 12 ms
0010 = 24 ms (default)
… (Time doubles with every step)
1010 = 6.144 sec