Datasheet

Data Sheet SSM2603
Rev. C | Page 21 of 32
RIGHT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x01
Table 13. Right-Channel ADC Input Volume Register Bit Map
D8 D7 D6 D5 D4 D3 D2 D1 D0
RLINBOTH
RINMUTE
0
RINVOL[5:0]
Table 14. Descriptions of Right-Channel ADC Input Volume Register Bits
Bit Name Description Settings
RLINBOTH Right-to-left line input ADC data load control 0 = disable simultaneous loading of right-channel ADC data to left-
channel register (default)
1 = enable simultaneous loading of right-channel ADC data to left-
channel register
RINMUTE Right-channel input mute 0 = disable mute
1 = enable mute on data path to ADC (default)
RINVOL[5:0] Right-channel PGA volume control 00 0000 = −34.5 dB
… In 1.5 dB steps
01 0111 = 0 dB (default)
… In 1.5 dB steps
01 1111 = 12 dB
10 0000 = 13.5 dB
10 0001 = 15 dB
10 0010 = 16.5 dB
10 0011 = 18 dB
10 0100 = 19.5 dB
10 0101 = 21 dB
10 0110 = 22.5 dB
10 0111 = 24 dB
10 1000 = 25.5 dB
10 1001 = 27 dB
10 1010 = 28.5 dB
10 1011 = 30 dB
10 1100 = 31.5 dB
10 1101 to 11 1111 = 33 dB