Datasheet

SSM2603 Data Sheet
Rev. C | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Digital Filter Characteristics ....................................................... 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Converter Filter Response ........................................................... 9
Digital De-Emphasis .................................................................. 10
Theory of Operation ...................................................................... 11
Digital Core Clock ...................................................................... 11
ADC and DAC ............................................................................ 11
ADC High-Pass and DAC De-Emphasis Filters .................... 11
Hardware Mute Pin .................................................................... 11
Automatic Level Control (ALC) ............................................... 12
Analog Interface ......................................................................... 13
Digital Audio Interface .............................................................. 15
Software Control Interface ........................................................ 17
Control Register Sequencing .................................................... 17
Typical Application Circuits ......................................................... 18
Register Map ................................................................................... 19
Register Map Details ...................................................................... 20
Left-Channel ADC Input Volume, Address 0x00 .................. 20
Right-Channel ADC Input Volume, Address 0x01 ............... 21
Left-Channel DAC Volume, Address 0x02 ............................. 22
Right-Channel DAC Volume, Address 0x03 .......................... 22
Analog Audio Path, Address 0x04 ........................................... 23
Digital Audio Path, Address 0x05 ............................................ 23
Power Management, Address 0x06 .......................................... 24
Digital Audio I/F, Address 0x07 ............................................... 25
Sampling Rate, Address 0x08 .................................................... 25
Active, Address 0x09 .................................................................. 28
Software Reset, Address 0x0F ................................................... 28
ALC Control 1, Address 0x10 ................................................... 29
ALC Control 2, Address 0x11 ................................................... 29
Noise Gate, Address 0x12 .......................................................... 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
REVISION HISTORY
6/13—Rev. B to Rev. C
Changes to Table 8 ............................................................................ 7
4/12—Rev. A to Rev. B
Changes to Figure 1 .......................................................................... 1
Changes to Stereo Line and Monaural Microphone Inputs
Section and Figure 20 ..................................................................... 13
Changes to Table 10 ........................................................................ 19
Changes to Table 19 and Table 20 ................................................ 23
Updated Outline Dimensions ....................................................... 31
Changes to Ordering Guide .......................................................... 31
8/09—Rev. 0 to Rev. A
Changes to General Description Section and Figure 1 ............... 1
Changes to Specifications Section, Table 1 ................................... 3
Changes to Master Clock Tolerance, Frequency Range
Parameter, Table 2 ............................................................................. 4
Added Endnote 1, Table 2 ................................................................ 4
Changes to Table 6 ............................................................................. 6
Changes to Figure 6 and Table 9...................................................... 8
Changes to Digital Core Clock Section ....................................... 11
Changes to Digital Audio Data Sampling Rate Section ............ 15
Changes to Figure 31...................................................................... 18
Added Control Register Sequencing Section.............................. 17
Change to Table 10 ......................................................................... 19
Changes to Table 15, Table 16, Table 17, and Table 18 .............. 22
Changes to Table 37 ....................................................................... 29
Added Exposed Pad Notation to Outline Dimensions ............. 31
2/08—Revision 0: Initial Version