Datasheet

REF19x Series Data Sheet
Rev. L | Page 22 of 28
management should still be exercised. A short, heavy, low dc
resistance (DCR) conductor should be used from U1 to 6 to the V
OUT
Sense Point S, where the collector of Q1 connects to the load, Point F.
Because of the current limiting configuration, the dropout voltage
circuit is raised about 1.1 V over that of the REF19x devices, due to
the V
BE
of Q1 and the drop across Current Sense Resistor R4.
However, overall dropout is typically still low enough to allow
operation of a 5 V to 3.3 V regulator/reference using the REF196 for
U1 as noted, with a V
S
as low as 4.5 V and a load current of 150 mA.
The requirement for a heat sink on Q1 depends on the maximum
input voltage and short-circuit current. With V
S
= 5 V and a
300 mA current limit, the worst-case dissipation of Q1 is 1.5 W,
less than the TO-220 package 2 W limit. However, if smaller TO-39
or TO-5 package devices, such as the 2N4033, are used, the current
limit should be reduced to keep maximum dissipation below
the package rating. This is accomplished by simply raising R4.
A tantalum output capacitor is used at C1 for its low equivalent
series resistance (ESR), and the higher value is required for stability.
Capacitor C2 provides input bypassing and can be an ordinary
electrolytic.
Shutdown control of the booster stage is an option, and when used,
some cautions are needed. Due to the additional active devices
in the V
S
line to U1, a direct drive to Pin 3 does not work as with an
unbuffered REF19x device. To enable shutdown control, the
connection from U1 to Q2 is broken at the X, and Diode D1
then allows a CMOS control source, V
C
, to drive U1 to 3 for on/off
operation. Startup from shutdown is not as clean under heavy
load as it is in basic REF19x series, and can require several
milliseconds under load. Nevertheless, it is still effective and
can fully control 150 mA loads. When shutdown control is
used, heavy capacitive loads should be minimized.
NEGATIVE PRECISION REFERENCE WITHOUT
PRECISION RESISTORS
In many current-output CMOS DAC applications where the output
signal voltage must be the same polarity as the reference voltage, it
is often necessary to reconfigure a current-switching DAC into
a voltage-switching DAC using a 1.25 V reference, an op amp,
and a pair of resistors. Using a current-switching DAC directly
requires an additional operational amplifier at the output to
reinvert the signal. A negative voltage reference is then desirable
because an additional operational amplifier is not required for
either reinversion (current-switching mode) or amplification
(voltage-switching mode) of the DAC output voltage. In general,
any positive voltage reference can be converted into a negative
voltage reference using an operational amplifier and a pair of
matched resistors in an inverting configuration. The disadvantage
to this approach is that the largest single source of error in the
circuit is the relative matching of the resistors used.
The circuit illustrated in Figure 26 avoids the need for tightly
matched resistors by using an active integrator circuit. In this
circuit, the output of the voltage reference provides the input
drive for the integrator. To maintain circuit equilibrium, the
integrator adjusts its output to establish the proper relationship
between the V
OUT
and GND references. Thus, any desired negative
output voltage can be selected by substituting for the appropriate
reference IC. The sleep feature is maintained in the circuit with
the simple addition of a PNP transistor and a 10 kΩ resistor.
100Ω
1µF
1kΩ
1µF
–V
REF
REF19x
V
S
GND
OUTPUT
100kΩ
SLEEP
TTL/CMOS
A1 = 1/2 OP295,
1/2 OP291
V
S
10kΩ
2N3906
3 6
2
4
SLEEP
10kΩ
+5V
–5V
A1
00371-024
Figure 26. Negative Precision Voltage Reference Uses No Precision Resistors
One caveat to this approach is that although rail-to-rail output
amplifiers work best in the application, these operational amplifiers
require a finite amount (mV) of headroom when required to provide
any load current; consider this issue when choosing the negative
supply for the circuit.
STACKING REFERENCE ICs FOR ARBITRARY
OUTPUTS
Some applications may require two reference voltage sources that
are a combined sum of standard outputs. The circuit in Figure 27
shows how this stacked output reference can be implemented.
Two reference ICs are used, fed from a common unregulated input,
V
S
. The outputs of the individual ICs are connected in series, as
shown in Figure 27, which provide two output voltages, V
OUT1
and
V
OUT2
. V
OUT1
is the terminal voltage of U1, whereas V
OUT2
is the
sum of this voltage and the terminal voltage of U2. U1 and U2
are chosen for the two voltages that supply the required outputs
(see Table 1). If, for example, both U1 and U2 are REF192s, the
two outputs are 2.5 V and 5.0 V.
R1
3.9kΩ
(SEE TEXT)
C1
0.1µF
+V
S
V
S
> V
OUT2
+ 0.15V
V
IN
COMMON
V
OUT
COMMON
OUTPUT TABLE
U1/U2
REF192/REF192
REF192/REF194
REF192/REF195
V
OUT1
(V)
2.5
2.5
2.5
V
OUT2
(V)
5.0
7.0
7.5
+V
OUT2
C2
1µF
C3
0.1µF
+V
OUT1
C4
1µF
U2
REF19x
(SEE TABLE)
2
63
4
U1
REF19x
(SEE TABLE)
2
63
4
+
+
V
O
(U2)
V
O
(U1)
00371-025
Figure 27. Stacking Voltage References with the REF19x