Datasheet

OP177A OP177B
Parameter Symbol Conditions Min Typ Max Min Typ Max Units
Input Offset Voltage V
OS
410 1025µV
Long-Term Input Offset Voltage Stability ∆V
OS
/Time (Note 1) 0.2 0.2 µV/Mo
Input Offset Current I
OS
0.3 1.0 0.3 1.5 nA
Input Bias Current I
B
–0.2 1.5 –0.2 2.0 nA
Input Noise Voltage e
n
f
o
= 1 Hz to 100 Hz
2
118 150 118 150 nV rms
Input Noise Current i
n
f
o
= 1 Hz to 100 Hz
2
38 38pA rms
Input Resistance Differential-Mode R
IN
(Note 3) 26 45 26 45 MΩ
Input Resistance Common-Mode R
INCM
200 200 GΩ
Input Voltage Range IVR (Note 4) ±13 ±14 ±13 ±14 V
Common-Mode Rejection Ratio CMRR V
CM
= ±13 V 130 140 130 140 dB
Power Supply Rejection Ratio PSRR V
S
= ±3 V to ±18 V 120 125 115 125 dB
Large Signal Voltage Gain A
VO
R
L
≥ 2 kΩ, V
O
= ±10 V
5
5000 12000 5000 12000 V/mV
Output Voltage Swing V
O
R
L
≥ 10 kΩ±13.5 ±14.0 ±13.5 ±14.0 V
R
L
≥ 2 kΩ±12.5 ±13.0 ±12.5 ±13.0 V
R
L
≥ 1 kΩ±12.0 ±12.5 ±12.0 ±12.5 V
Slew Rate SR R
L
≥ 2 kΩ
2
0.1 0.3 0.1 0.3 V/µs
Closed-Loop Bandwidth BW A
VCL
= +1
2
0.4 0.6 0.4 0.6 MHz
Open-Loop Output Resistance R
O
60 60 Ω
Power Consumption P
D
V
S
= ±15 V, No Load 50 60 50 60 mW
V
S
= ±3 V, No Load 3.5 4.5 3.5 4.5 mW
Supply Current I
SY
V
S
= ±15 V, No Load 1.6 2.0 1.6 2.0 mA
Offset Adjustment Range Rp = 20 kΩ ±3 ±3mV
NOTES
1
Long-Term Input Offset Voltage Stability refers to the averaged trend line of V
OS
vs. Time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in V
OS
during the first 30 operating days are typically less than 2.0 µV.
2
Sample tested.
3
Guaranteed by design.
4
Guaranteed by CMRR test condition.
5
To insure high open-loop gain throughout the ±10 V output range, A
VO
is tested at –10 V ≤ V
O
≤ 0 V, 0 V ≤ V
O
≤ +10 V, and –10 V ≤ V
O
≤ +10 V.
Specifications subject to change without notice.
REV. B
–2–
OP177–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ V
S
= 615 V, T
A
= +258C, unless otherwise noted)
ELECTRICAL CHARACTERISTICS
OP177A OP177B
Parameter Symbol Conditions Min Typ Max Min Typ Max Units
Input Offset Voltage V
OS
10 20 25 55 µV
Average Input Offset Voltage Drift TCV
OS
(Note 1) 0.03 0.1 0.1 0.3 µV/°C
Input Offset Current I
OS
0.5 1.5 0.5 2.0 nA
Average Input Offset Current Drift TCI
OS
(Note 2) 1.5 25 1.5 25 pA/°C
Input Bias Current I
B
–0.2 2.4 4 –0.2 2.4 4 nA
Average Input Bias Current Drift TCI
B
(Note 2) 8 25 8 25 pA/°C
Input Voltage Range IVR (Note 3) ±13 ±13.5 ±13 ±13.5 V
Common-Mode Rejection Ratio CMRR V
CM
= ±13 V 120 140 120 140 dB
Power Supply Rejection Ratio PSRR V
S
= ±3 V to ±18 V 120 125 110 120 dB
Large-Signal Voltage Gain A
VO
R
L
≥ 2 kΩ, V
O
= ±10 V
4
2000 6000 2000 6000 V/mV
Output Voltage Swing V
O
R
L
≥ 2 kΩ±12 ±13.0 ±12 ±13.0 V
Power Consumption P
D
V
S
= ±15 V, No Load 60 75 60 75 mW
Supply Current I
SY
V
S
= ±15 V, No Load 2.0 2.5 2.0 2.5 mA
NOTES
1
TCV
OS
is 100% tested.
2
Guaranteed by endpoint limits.
3
Guaranteed by CMRR test condition.
4
To insure high open-loop gain throughout the ±10 V output range, A
VO
is tested at –10 V ≤ V
O
≤ 0 V, 0 V ≤ V
O
≤ +10 V, and –10 V ≤ V
O
≤ +10 V.
Specifications subject to change without notice.
(@ V
S
= 615 V, –55°C ≤ T
A
≤ +1258C, unless otherwise noted)