Datasheet

OP177 Data Sheet
Rev. H | Page 4 of 16
At V
S
= ±15 V, −40°C ≤ T
A
≤ +85°C, unless otherwise noted.
Table 2.
OP177F OP177G
Parameter Symbol Test Conditions/Comments Min Typ Max Min Typ Max Unit
INPUT
Input Offset Voltage V
OS
15 40 20 100 μV
Average Input Offset Voltage Drift
1
TCV
OS
0.1 0.3 0.7 1.2 μV/°C
Input Offset Current I
OS
0.5 2.2 0.5 4.5 nA
Average Input Offset Current Drift
2
TCI
OS
1.5 40 1.5 85 pA/°C
Input Bias Current I
B
−0.2 +2.4 +4 +2.4 ±6 nA
Average Input Bias Current Drift
2
TCI
B
8 40 15 60 pA/°C
Input Voltage Range
3
IVR ±13 ±13.5 ±13 ±13.5 V
COMMON-MODE REJECTION RATIO CMRR V
CM
= ±13 V 120 140 110 140 dB
POWER SUPPLY REJECTION RATIO PSRR V
S
= ±3 V to ±18 V 110 120 106 115 dB
LARGE-SIGNAL VOLTAGE GAIN
4
A
VO
R
L
≥ 2 kΩ, V
O
= ±10 V 2000 6000 1000 4000 V/mV
OUTPUT VOLTAGE SWING V
O
R
L
≥ 2 kΩ ±12 ±13 ±12 ±13 V
POWER CONSUMPTION P
D
V
S
= ±15 V, no load 60 75 60 75 mW
SUPPLY CURRENT I
SY
V
S
= ±15 V, no load 20 2.5 2 2.5 mA
1
TCV
OS
is sample tested.
2
Guaranteed by endpoint limits.
3
Guaranteed by CMRR test condition.
4
To ensure high open-loop gain throughout the ±10 V output range, A
VO
is tested at −10 V ≤ V
O
≤ 0 V, 0 V ≤ V
O
≤ +10 V, and −10 V ≤ V
O
≤ +10 V.
TEST CIRCUITS
200k
Ω
50Ω
V
OS
=
V
O
4000
V
O
00289-003
OP177
–
+
Figure 3. Typical Offset Voltage Test Circuit
OP177
V+
OUTPUT
–
+
–
+
INPUT
V–
20kΩ
V
OS
TRIM RANGE IS
TYPICALLY ±3.0mV
00289-004
Figure 4. Optional Offset Nulling Circuit
OP177
–
+
PINOUTS SHOWN FOR
P AND Z PACKAGES
0
0289-005
+20V
–20V
20kΩ
Figure 5. Burn-In Circuit