Datasheet

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POWER CONDITIONING - SMT
12
HMC1060LP3E
v00.1211
QUAD LOW NOISE HIGH PSRR
LINEAR VOLTAGE REGULATOR
R1, R2, and band-gap voltage VREF are provided in the Output Conguration Table, and where VRx (x = 1,2,3,4) is
the desired output voltage level of each HMC1060LP3E output, as measured at the output pin.
2
2
1
1
11
Y
VRx
R
VREF
R
R
VRx
R VREF



=

−−


(EQ 1)
Output Conguration Table
Output PTAT Mode R1 (k) R2 (k) R3 (k)
[1]
VREF (V)
VR1, VR2, VR3
Disabled 50 2 7.4 34.6 1.17
Enabled 50 35.5 34.6 1.37
VR4
Disabled 59 18 N/A 1.17
Enabled 59 22 N/A 1.37
[1] Internal resistor R3 exists between pins RD1 and HV1, between RD2 and HV2, and between RD3 and HV3. Internal resistances R1, R2,
and R3 have a temperature coefficient of +270 ppm/°C. When using external resistances to congure the HMC1060LP3E to non-default output
voltages it may be benecial to use the R3 resistance value in order to achieve a desired resistance Rx when conguring VR1, VR2, and/or VR3
outputs to voltages greater than default value (3.3 V)
Supply Voltage Greater Than Default Conguration
To congure any or all of the VR1, VR2, and VR3 outputs of the HMC1060LP3E to supply 5 V, connect the appropriate
HV pin (HV1, HV2, and HV3 corresponding to outputs VR1, VR2, VR3 respectively) of the HMC1060LP3E to ground,
as shown in Figure 15. This output conguration is only supported if PTAT Mode is disabled.
Figure 15.
Recommended HMC1060LP3E conguration for supplying 5 V at the output of VR1 pin.
[3]
Other output voltages values that are greater than the default value are achieved by using and external resistor Rx as
shown in Figure 16. Output conguration in Figure 16 supports both PTAT mode enabled and disabled.
[3] Other outputs (VR2 and VR3) are not shown in this example, but are congured for 5 V output in exactly the same way. VDD input is limited to 5.6
V maximum and 5.3 V minimum.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
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