Datasheet

Evaluation Board User Guide UG-253
Rev. A | Page 7 of 16
COMMAND REGISTER
The Command Register section of the AD7291 data sheet
should be consulted before configuring the control register
settings. To configure the command register, click COMMAND
REGISTER (see Figure 4).
09710-005
Figure 5. Command Register
Select the ADC channels required for conversion in the
sequence. To enable the internal temperature sensor, select
DB7/TSENSE.
When DB5/NOISE DELAYED BIT TRIAL SAMPLING is
enabled, critical sampling intervals and bit trials are delayed
when there is activity on the I
2
C bus, thus ensuring improved
dc performance of the AD7291.
The active polarity of the ALERT pin is configured as active low
if the DB3/POLARITY OF ALERT PIN is enabled. Conversely,
it is set to active high operation if this bit is disabled.
DB2/CLEAR ALERT clears the content of the alert status
register. Once the content of the alert status register is cleared,
this bit should be reprogrammed to Logic 0 to ensure future
alerts are detected.
Enabling the DB1/RESET bit in the command register resets the
content of all internal registers in the AD7291 to their default
values, including the command register itself. Disable
this bit once the reset is complete to allow the internal registers
to be reprogrammed.
The DB0/AUTOCYCLE MODE enables autocycle mode. In
autocycle mode, the AD7291 is configured to convert continu-
ously on the selected sequence of channels (both analog input
channels and the temperature sensor channel), making it the
ideal mode of operation for system monitoring. While in this
mode, the conversion results from the analog input channels are
not displayed on the user interface.
Click WRITE to update the control register.
ALERT LIMITS
The AD7291 has nine pairs of limit registers. Each pair stores
high and low conversion limits for each analog input channel
and the internal temperature sensor. Each pair of limit registers
has one associated hysteresis register. To program the alert
limits and associated hysteresis register, click ALERT LIMITS
SETUP on the main window.
09710-006
Figure 6. Alert Limits Setup
The AD7291 signals an alert in hardware if the conversion
result moves outside the upper or lower limit set by the limit
registers. ALERTA and ALERTB indicators on the main
window turn red if a limit is violated, as shown in Figure 7.
Alert Register A stores alerts for the analog voltage conversion
channels, and Alert Register B stores alerts for the internal
temperature sensor.
For further information on the status of the alerts, click READ
ALERT STATUS on the front panel. For example, Figure 8
depicts an example where the V
IN0
low limit, TSENSE AVG high
limit, and TSENSE high limit have been violated.
SAMPLE ADC/CONTINUOUSLY SAMPLE
To gather sample data on the selected channels, click SAMPLE
ADC or CONTINUOUSLY SAMPLE. Both buttons are located
on the upper middle area of the main window. To stop
sampling, click CONTINOUSLY SAMPLE a second time.