Datasheet

Evaluation Board User Guide UG-253
Rev. A | Page 3 of 16
EVALUATION BOARD HARDWARE
POWER SUPPLIES
Care should be taken before applying power and signals to the
evaluation board to ensure that all link positions are as required
by the operating mode.
When using this evaluation board with the SDP board, apply
+5 V, −5 V, and GND to Connector J2. V
DRIVE
is supplied by
the SDP board, and V
DD
is supplied by an on-board regulator.
Each supply is decoupled on the EVAL -AD7291SDZ using
10 µF and 0.1 µF capacitors. A single ground plane is used on
this board to minimize the effect of high frequency noise
interference.
LINK OPTIONS
Table 1 shows the position in which all the links are set when
the evaluation board is packaged. The links are set so that
control signals and V
DRIVE
are supplied by the SDP board.
Multiple link (LKx) and solder link (SLx) options must be set
correctly to select the appropriate operating setup before using
the evaluation board. The default link positions are shown in
Table 1 and the functions of these options are outlined in Table 2.
Table 1. Link Options
Link No. Position Function
LK1 Inserted This link option pulls the AD7291 V
IN0
input to GND via a 10 kΩ resistor.
LK2 Inserted This link option pulls the AD7291 V
IN1
input to GND via a 10 kΩ resistor.
LK3 Inserted This link option pulls the AD7291 V
IN6
input to GND via a 10 kΩ resistor.
LK4 Inserted This link option pulls the AD7291 V
IN7
input to GND via a 10 kΩ resistor.
LK5 Position A
Connects the PD/RST pin to V
DRIVE
voltage.
LK6 Position A When in Position A, the 3.3 V V
CC
supply is supplied by the on-board regulator, ADP1706.
LK7 Position A When in Position A, the V
DRIVE
supply is taken from the SDP board via VIO_CONNECTOR.
LK8 Inserted When inserted, the V
REF
signal is connected to the V
REF
test point.
LK9 Inserted
When inserted, the buffered internal reference voltage is divided by a factor of 3 and used as the
bias input for U10.
LK10 Inserted This link option pulls the AD7291 V
IN2
input to GND via a 10 kΩ resistor.
LK11 Inserted This link option pulls the AD7291 V
IN3
input to GND via a 10 kΩ resistor.
LK12 Inserted This link option pulls the AD7291 V
IN4
input to GND via a 10 kΩ resistor.
LK13 Inserted This link option pulls the AD7291 V
IN5
input to GND via a 10 kΩ resistor.
LK14 Inserted This link option connects +5 V to Pin 1 of J1.
LK20 Position A In Position A, the buffered internal reference is used as the bias input for U10.
SL1 Position B Buffered output from SMA Connector V7 is routed to SMB Connector BUFF_V7.
SL2 Position A In Position A, there is no amplifier included in the Analog Input Channel V
IN1
path.
SL3 Position B Buffered output from SMA Connector V0 is routed to SMB Connector BUFF_V0.
SL4 Position B In Position B, there is an amplifier included on the Analog Input Channel V
IN0
path.