Datasheet

EVAL-AD7265/AD7266
Rev. 0 | Page 5 of 24
Link No. Description
LK16 This link option sets the output reference voltage delivered by the AD780.
When this link is inserted, the AD780 output voltage is set to +3.0 V.
When this link is removed, the AD780 output voltage is set to +2.5 V.
LK17 This link option selects the source of the V
DRIVE
supply for the AD7265/AD7266.
In Position A, V
DRIVE
is supplied from the EVAL-CED1Z. The value of V
DRIVE
in this case is 3.3 V.
In Position B, the V
DRIVE
supply must be supplied from an external source via J3. Note that the logic interface on the EVAL-CED1Z
operates at 3.3 V.
LK18 Not populated.
LK19 This link option selects the logic input to the REF SELECT pin.
In Position A, the REF SELECT pin is tied to V
DRIVE
(Logic 1). Therefore, an external reference must be supplied through the
D
CAP
A/D
CAP
B pins.
In Position B, the REF SELECT pin is tied to DGND (Logic 0). Therefore, the internal on-chip 2.5 V reference is used.
LK20 This link option selects the logic input to the RANGE pin.
In Position A, the RANGE pin is tied to V
DRIVE
(Logic 1). Therefore, the device is configured for an analogue input range of 0 V
to 2 V
REF
.
In Position B, the RANGE pin is tied to DGND (Logic 0). Therefore, the analogue input range is 0 V to V
REF
.
LK21 This link option selects the logic input to the SGL/
DIFF
pin.
In Position A, the ADC is tied to V
DRIVE
and, therefore, the ADC is configured to operate in single-ended mode.
In Position B, the ADC is tied to DGND and, therefore, the ADC is configured to operate in differential mode.
LK22 This link option selects the source of the logic input to the A0 pin. It should be used in conjunction with LK23 and LK24 to
determine the pair of channels to be simultaneously converted.
In Position A, the A0 pin is tied to a V
DRIVE
, a high logic level.
In Position B, the logic level applied to the A0 pin is controlled via the channel selection option in the software.
In Position C, the A0 pin is tied to DGND, a low logic level.
In Position D, an external A0 logic level can be applied through the external socket, J6.
LK23 This link option selects the source of the logic input to the A1 pin; it should be used in conjunction with LK22 and LK24, to
determine the pair of channels to be simultaneously converted.
In Position A, the A1 pin is tied to V
DRIVE
, a high logic level.
In Position B, the logic level applied to A1 is controlled via the channel selection icon in the software.
In Position C, the A1 pin is tied to DGND, a low logic level.
In Position D, an external A1 logic level can be applied through the external socket, J7.
LK24 This link option selects the source of the logic input to the A2 pin; it should be used in conjunction with LK22 and LK23 to
determine the pair of channels to be simultaneously converted.
In Position A, the A2 pin is tied to V
DRIVE
, a high logic level.
In Position B, the logic level applied to A1 is controlled via the channel selection option in the software.
In Position C, the A2 pin is tied to DGND, a low logic level.
In Position D, an external A2 value can be applied through the external socket, J8.
LK25 This link option selects the source of the
CS
input.
In Position A, the
CS
input is provided by the EVAL-CED1Z.
In Position B, the
CS
input is provided via the external SMB socket, J9.
LK26 Not populated.
LK27 This link option selects the source of the SCLK input.
In Position A, the SCLK input is provided via the external SMB socket, J10.
In Position B, the SCLK input is provided by the EVAL-CED1Z.
LK28 This link option selects the destination of the serial data output (D
OUT
A).
In Position A, the data is supplied to the EVAL-CED1Z.
In Position B, the data is supplied to the external SMB socket, J11.
LK29 This link option selects the destination of the serial data output (D
OUT
B).
In Position A, the data is supplied to the EVAL-CED1Z.
In Position B, the data is supplied to the external SMB socket, J12.
LK30 Not populated.