Datasheet

EVAL-AD7262/AD7264
Rev. 0 | Page 4 of 20
Link No. Function
LK8
This link option selects the source of the logic input to the PD1 pin, thus selecting the power-down configuration for the
AD7262 or AD7264.
In Position A, the PD1 pin is connected to the V
DRIVE
supply, that is, it is tied to a logic high state.
In Position B, PD1 is supplied by the EVAL-CED1Z board.
In Position C, the PD1 pin is connected to DGND, that is, it is tied to a logic low state.
LK9
This link option selects the source of the logic input to the PD2 pin, thus selecting the power down configuration for the
AD7262 or AD7264.
In Position A, the PD2 pin is connected to the V
DRIVE
supply, that is, it is tied to a logic high state.
In Position B, the PD2 pin is supplied by the EVAL-CED1Z board.
In Position C, the PD2 pin is connected to DGND, that is, it is tied to a logic low state.
LK10 This link option selects the source of the logic input to the G0 pin, thus selecting the gain of the AD7262 or AD7264.
In Position A, the G0 pin is connected to the V
DRIVE
supply, that is, it is tied to a logic high state.
In Position B, the G0 pin is supplied by the EVAL-CED1Z board.
In Position C, the G0 pin is connected to DGND, that is, it is tied to a logic low state.
LK11 This link option selects the source of the logic input to the G1 pin, thus selecting the gain of the AD7262 or AD7264.
In Position A, the G1 pin is connected to the V
DRIVE
supply, that is, it is tied to a logic high state.
In Position B, the G1 pin is supplied by the EVAL-CED1Z board.
In Position C, the G1 pin is connected to DGND, that is, it is tied to a logic low state.
LK12 This link option selects the source of the logic input to the G2 pin, thus selecting the gain of the AD7262 or AD7264
In Position A, the G2 pin is connected to the V
DRIVE
supply, that is, it is tied to a logic high state.
In Position B, the G2 pin is supplied by the EVAL-CED1Z board.
In Position C, the G2 pin is connected to DGND, that is, it is tied to a logic low state.
LK13 This link option selects the source of the logic input to the G3 pin, thus selecting the gain of the AD7262 or AD7264
In Position A, the G3 pin is connected to the V
DRIVE
supply, that is, it is tied to a logic high state.
In Position B, the G3 pin is supplied by the EVAL-CED1Z board.
In Position C, the G3 pin is connected to DGND, that is, it is tied to a logic low state.
LK14 This link option is used to select the source of the +12 V supply, which is used to power the external reference.
In Position A, +12 V is supplied from the EVAL-CED1Z board through the 96-way connector.
In Position B, +12 V is supplied from an external source via the power connector, J17.
SL1 This link option selects the source of one of the AV
CC
supplies for the AD7262 or AD7264.
In Position A, AV
CC
is tied to the other AV
CC
supply.
In Position B, AV
CC
is supplied from an external source via J5-3 SMB. This option should not be used.
SL2, SL3 These link options select the source of the C
A
_C
B
V
CC
and C
C
_C
D
V
CC
supplies for the AD7262/AD7264.
In Position A, C
A
_C
B
V
CC
and C
C
_C
D
V
CC
are tied to the AVCC supply.
In Position B, C
A
_C
B
V
CC
and C
C
_C
D
V
CC
are supplied from an external source via C
A
_C
B
V
CC
and C
C
_C
D
V
CC
SMB.
SL4 This link selects the source of the SCLK signal for the AD7262 or AD7264.
In Position A, the SCLK signal is taken directly from the EVAL-CED1Z board through the 96-way connector.
In Position B, the SCLK signal must be supplied from an external source via the SCK SMB.
SL5
This link in conjunction selects the source of the CS
input to the ADC.
In Position A, CS
is supplied by the EVAL-CED1Z board.
In Position B, CS
is supplied from an external source via the CS SMB.
R12, R13 These resistors must be inserted if the D
OUT
A and D
OUT
B signal as to be fed to the DOUT-A, DOUT-B SMB.