Datasheet

EVAL-AD7262/AD7264
Rev. 0 | Page 3 of 20
EVALUATION BOARD HARDWARE
POWER SUPPLIES
When using this evaluation board with the EVAL-CED1Z,
all supplies are provided from the EVAL-CED1Z through the
96-way connector. When using the board as a standalone unit,
external supplies must be provided. This evaluation board has
the following power supply inputs: +12 V, AV
CC
(+5 V), AGND,
V
DRIVE
, and DGND. The (+12 V) supply is only required if the
external AD780 voltage reference is to be used, however if the
AD7262 or AD7264 is used with an internal reference then the
±12 V supplies are not required.
The supplies are decoupled to the relevant ground plane with
10 μF tantalum and 0.1 μF multilayer ceramic capacitors at
the point where they enter the board. The supply pins for the
external reference are also decoupled to AGND with a 10 μF
tantalum and a 0.1 μF ceramic capacitor. The AV
CC
, C
A
_C
B
V
CC
and C
C
_C
D
V
CC
supply pins are decoupled to AGND with a
0.1 μF multilayer ceramic capacitors per supply pin and one
10 μF tantalum capacitor for all the previously mentioned
supply pins.
Extensive ground planes are used on this board to minimize
the effect of high frequency noise interference. There are two
ground planes, AGND and DGND. These are connected at one
location close to the AD7262 or AD7264.
LINK OPTIONS
There are 14 link options and 5 solder links that must be set
correctly to select the appropriate operating setup before using
the evaluation board. The functions of these options are
outlined in Table 1.
The evaluation board also contains two resistor links which
enable the user to access the digital output from the part via the
SMB connectors. In normal operation with the EVAL-CED1Z
board these resistors are not inserted and the output from the
AD7262 or AD7264 is fed directly to the EVAL-CED1Z board
for processing.
Table 1. Link Option Functions
Link No. Function
LK1, LK2 These links select the source of the reference input voltage applied to the V
REF
A and V
REF
B pins of the AD7262 and AD7264.
In Position A, the reference input must be supplied through the V
REF
A and V
REF
B SMB connectors if the internal reference on
the AD7264 and AD7262 is not used.
In Position B, the AD780 supplies a 2.5 V reference to the AD7262 or AD7264.
LK3 This link selects whether the AD7262 or AD7264 uses the internal or external reference by setting the logic state of the REFSEL pin.
In Position A, the on-chip 2.5 V internal reference is used as the reference source for both ADC A and ADC B. In this case, LK1
and LK2 can be left unconnected.
In Position B, an external reference can be supplied to the AD7262 or AD7264 through the V
REF
A or V
REF
B pins. In this case, LK1
and LK2 must be in Position A or Position B.
LK4 This link option selects the source of the V
DRIVE
supply for the AD7262 or AD7264 digital interface.
In Position A, a 3.3 V V
DRIVE
input is supplied to the AD7264 or AD7262 from the EVAL-CED1Z board.
In Position B, the V
DRIVE
input on the AD7264 or AD7262 is tied to the AV
CC
supply.
In Position C, V
DRIVE
must be supplied from an external source via the J5-1 SMB.
LK5 This link option selects the source of the AV
CC
supply for the AD7262 or AD7264.
In Position A, AV
CC
is supplied from the EVAL-CED1Z board.
In Position B, AV
CC
must be supplied from an external source via the J6-1 SMB connector.
LK6 This link option selects the source of the logic input to the CAL pin, thus selecting the gain of the AD7262 or AD7264.
In Position A, the CAL pin is connected to the V
DRIVE
supply, that is, it is tied to a logic high state.
In Position B, the CAL pin is supplied by the EVAL-CED1Z board.
In Position C, the CAL pin is connected to DGND, that is, it is tied to a logic low state.
LK7
This link option selects the source of the logic input to the PD0/D
IN
pin, thus selecting the power-down configuration for the
AD7262 or AD7264.
In Position A, the PD0/D
IN
pin is connected to the V
DRIVE
supply. That is, it is tied to a logic high state.
In Position B, the PD0/D
IN
pin is supplied by the EVAL-CED1Z board.
In Position C, the PD0/D
IN
pin is connected to DGND, that is, it is tied to a logic low state.
Position D should not be selected.