Datasheet

AD7091 Data Sheet
Rev. A | Page 4 of 20
Parameter Test Conditions/Comments Min Typ Max Unit
Power Dissipation V
IN
= 0 V
Normal Mode—Static
4
V
DD
= 5.25 V 50 142 µW
V
DD
= 3 V 27 84 µW
Normal Mode—Operational V
DD
= 5.25 V, f
SAMPLE
= 1 MSPS 2.4 3 mW
V
DD
= 3 V, f
SAMPLE
= 1 MSPS
1.1
1.4
mW
Power-Down Mode V
DD
= 5.25 V 2 44 µW
V
DD
= 3 V 1 24 µW
1
Dynamic performance is achieved when SCLK operates in burst mode. Operating a free running SCLK during the acquisition phase degrades dynamic performance.
2
See the Terminology section.
3
Sample tested during initial release to ensure compliance.
4
SCLK is operating in burst mode and
CS
is idling high. With a free running SCLK and
CS
pulled low, the I
DD
static current is increased by 60 µA typical at V
DD
= 5.25 V.
TIMING SPECIFICATIONS
V
DD
= 2.09 V to 5.25 V, T
A
= −40°C to +125°C, unless otherwise noted. Signals are specified from 10% to 90% of V
DD
with a load
capacitance of 12 pF on the output pin.
1
Table 2.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
SCLK
50 MHz max Frequency of serial read clock
t
1
8 ns max Delay from the end of a conversion until SDO exits the three-state condition
t
2
7 ns max Data access time after SCLK falling edge
t
3
0.4 t
SCLK
ns min SCLK high pulse width
t
4
3 ns min SCLK to data valid hold time
t
5
0.4 t
SCLK
ns min SCLK low pulse width
t
6
15 ns max SCLK falling edge to SDO high impedance
t
7
10
ns min
CONVST
pulse width
t
8
650 ns max Conversion time
t
9
6 ns min
CS
low time before the end of a conversion
t
10
18 ns max Delay from
CS
falling edge until SDO exits the three-state condition
t
11
8 ns min
CS
high time before the end of a conversion
t
12
8 ns min Delay from the end of a conversion until the
CS
falling edge
t
13
100
µs max
Power-up time
t
QUIET
50 ns min Time between the last SCLK edge and the next
CONVST
pulse
1
Sample tested during initial release to ensure compliance.