Datasheet

AD7091 Data Sheet
Rev. A | Page 16 of 20
BUSY INDICATOR DISABLED
To operate the AD7091 without the busy indicator, a conversion
must first be started. A high-to-low transition on
CONVST
initi-
ates a conversion. This transition places the track-and-hold into
hold mode and samples the analog input at this point. If the user
does not want the AD7091 to enter power-down mode,
CONVST
should be taken high before the end of the conversion.
A conversion requires 650 ns to complete. When the conversion
process is finished, the track-and-hold returns to track mode. To
prevent the busy indicator from becoming enabled, ensure that
CS
is pulled high before the end of the conversion (see Figure 27).
The conversion result is shifted out of the device as a 12-bit
word under the control of SCLK and
CS
. The MSB (Bit DB11)
is clocked out on the falling edge of
CS
. DB10 to DB0 are shifted
out on the subsequent falling edges of SCLK. The 12
th
SCLK
falling edge returns SDO to a high impedance state. After all the
data is clocked out, pull
CS
high again. Data is propagated on
SCLK falling edges and is valid on both the rising and falling
edges of the next SCLK. The timing diagram for this operation
is shown in Figure 27.
If another conversion is required, pull
CONVST
low again and
repeat the cycle.
T
HRE
E-ST
ATE
THR
EE-
STA
TE
CS
SC
LK
1 5
122
3 4
DB11
DB
10 DB
9 DB
2 DB1
t
2
t
3
t
5
t
6
D
B8
DB
7
S
DO
CONVST
EOC
1
0 11
t
10
t
QUIET
t
7
t
8
t
4
t
11
DB0
t
12
NOTES
1. EOC IS THE END OF A CONVERSION.
10494-025
Figure 27. Serial Port Timing Without Busy Indicator